Jiangli Zhu

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cryptographic key management
- Patent number 12,182,318
- Issue date Dec 31, 2024
- Micron Technology, Inc.
- Juane Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Open translation unit management using an adaptive read threshold
- Patent number 12,176,060
- Issue date Dec 24, 2024
- Micron Technology, Inc.
- Murong Lang
- G11 - INFORMATION STORAGE
Information Patent Grant
Concurrent command limiter for a memory system
- Patent number 12,164,811
- Issue date Dec 10, 2024
- Micron Technology, Inc.
- Jason Duong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cell voltage level selection
- Patent number 12,165,709
- Issue date Dec 10, 2024
- Micron Technology, Inc.
- Tingjun Xie
- G11 - INFORMATION STORAGE
Information Patent Grant
Detect whether die or channel is defective to confirm temperature data
- Patent number 12,148,495
- Issue date Nov 19, 2024
- Micron Technology, Inc.
- Venkata Naga Lakshman Pasala
- G11 - INFORMATION STORAGE
Information Patent Grant
Write determination counter
- Patent number 12,147,708
- Issue date Nov 19, 2024
- Micron Technology, Inc.
- Seungjune Jeon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partition command queues for a memory device
- Patent number 12,093,564
- Issue date Sep 17, 2024
- Micron Technology, Inc.
- Juane Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing power loss in a memory device
- Patent number 12,086,062
- Issue date Sep 10, 2024
- Micron Technology, Inc.
- Huapeng G. Guan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer allocation for reducing block transit penalty
- Patent number 12,079,517
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory block programming using defectivity information
- Patent number 12,051,479
- Issue date Jul 30, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Selecting a write operation mode from multiple write operation modes
- Patent number 12,050,808
- Issue date Jul 30, 2024
- Micron Technology, Inc.
- Zhenlei Shen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double threshold controlled scheduling of memory access commands
- Patent number 12,039,196
- Issue date Jul 16, 2024
- Micron Technology, Inc.
- Jiangli Zhu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware based status collector acceleration engine for memory sub-...
- Patent number 12,019,915
- Issue date Jun 25, 2024
- Micron Technology, Inc.
- Fangfang Zhu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple-pass programming of memory cells using temporary parity ge...
- Patent number 12,001,721
- Issue date Jun 4, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified sequencer concurrency controller for a memory sub-system
- Patent number 11,971,772
- Issue date Apr 30, 2024
- Micron Technology, Inc.
- Fangfang Zhu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus with read level management and methods for operating the...
- Patent number 11,966,591
- Issue date Apr 23, 2024
- Micron Technology, Inc.
- Murong Lang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decreasing a quantity of queues to adjust a read throughput level f...
- Patent number 11,947,421
- Issue date Apr 2, 2024
- Micron Technology, Inc.
- Zhenming Zhou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing the programming of an open translation unit
- Patent number 11,923,001
- Issue date Mar 5, 2024
- Micron Technology, Inc.
- Murong Lang
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing an adjustable write-to-read delay based on cycle counts in...
- Patent number 11,914,889
- Issue date Feb 27, 2024
- Micron Technology, Inc.
- Murong Lang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock domain crossing queue
- Patent number 11,907,563
- Issue date Feb 20, 2024
- Micron Technology, Inc.
- Yueh-Hung Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduce read command latency in partition command scheduling at a me...
- Patent number 11,899,972
- Issue date Feb 13, 2024
- Micron Technology, Inc.
- Juane Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent command limiter for a memory system
- Patent number 11,893,280
- Issue date Feb 6, 2024
- Micron Technology, Inc.
- Jason Duong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Consolidating write request in cache memory
- Patent number 11,880,600
- Issue date Jan 23, 2024
- Micron Technology, Inc.
- Ning Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Open translation unit management using an adaptive read threshold
- Patent number 11,881,284
- Issue date Jan 23, 2024
- Micron Technology, Inc.
- Murong Lang
- G11 - INFORMATION STORAGE
Information Patent Grant
Scheduling of read operations and write operations based on a data...
- Patent number 11,874,779
- Issue date Jan 16, 2024
- Micron Technology, Inc.
- Wei Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maintaining data consistency in a memory sub-system that uses hybri...
- Patent number 11,874,769
- Issue date Jan 16, 2024
- Micron Technology, Inc.
- Ning Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing trim commands in a memory sub-system
- Patent number 11,868,642
- Issue date Jan 9, 2024
- Micron Technology, Inc.
- Yueh-Hung Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sub-system including an in-package sequencer to perform erro...
- Patent number 11,869,618
- Issue date Jan 9, 2024
- Micron Technology, Inc.
- Samir Mittal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Management unit based media management operations in memory devices
- Patent number 11,861,225
- Issue date Jan 2, 2024
- Micron Technology, Inc.
- Yueh-Hung Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Maintenance operations for memory devices
- Patent number 11,861,167
- Issue date Jan 2, 2024
- Micron Technology, Inc.
- Ning Chen
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
RELIABILITY IMPROVEMENTS USING MEMORY DIE BINNING
- Publication number 20250004647
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Ying Yu Tai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTITION COMMAND QUEUES FOR A MEMORY DEVICE
- Publication number 20240411484
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Juane Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFER ALLOCATION FOR REDUCING BLOCK TRANSIT PENALTY
- Publication number 20240393980
- Publication date Nov 28, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER-OFF MONITOR FOR RELAXED BLOCK RETIREMENT IN A MEMORY SUB-SYSTEM
- Publication number 20240393969
- Publication date Nov 28, 2024
- Micron Technology, Inc.
- Fanqi Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE BASED STATUS COLLECTOR ACCELERATION ENGINE FOR MEMORY SUB-...
- Publication number 20240377990
- Publication date Nov 14, 2024
- Micron Technology, Inc.
- Fangfang Zhu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION
- Publication number 20240347128
- Publication date Oct 17, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Application
PARTIALLY GOOD BLOCK HANDLING IN A MEMORY DEVICE
- Publication number 20240330094
- Publication date Oct 3, 2024
- Micron Technology, Inc.
- Yu-Chung Lien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE-PASS PROGRAMMING OF MEMORY CELLS USING TEMPORARY PARITY GE...
- Publication number 20240302999
- Publication date Sep 12, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS WITH TIME-BASED READ LEVEL MANAGEMENT AND METHODS FOR OPE...
- Publication number 20240231644
- Publication date Jul 11, 2024
- Micron Technology, Inc.
- Murong Lang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNIFIED SEQUENCER CONCURRENCY CONTROLLER FOR A MEMORY SUB-SYSTEM
- Publication number 20240219994
- Publication date Jul 4, 2024
- Micron Technology, Inc.
- Fangfang Zhu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REMAPPING BAD BLOCKS IN A MEMORY SUB-SYSTEM
- Publication number 20240192875
- Publication date Jun 13, 2024
- Micron Technology, Inc.
- Yang Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING THE PROGRAMMING OF AN OPEN TRANSLATION UNIT
- Publication number 20240170057
- Publication date May 23, 2024
- Micron Technology, Inc.
- Murong Lang
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCE READ COMMAND LATENCY IN PARTITION COMMAND SCHEDULING AT A ME...
- Publication number 20240143232
- Publication date May 2, 2024
- Micron Technology, Inc.
- Juane Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSOLIDATING WRITE REQUEST IN CACHE MEMORY
- Publication number 20240143231
- Publication date May 2, 2024
- Micron Technology, Inc.
- Ning Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONCURRENT COMMAND LIMITER FOR A MEMORY SYSTEM
- Publication number 20240126480
- Publication date Apr 18, 2024
- Micron Technology, Inc.
- Jason Duong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPEN TRANSLATION UNIT MANAGEMENT USING AN ADAPTIVE READ THRESHOLD
- Publication number 20240105240
- Publication date Mar 28, 2024
- Micron Technology, Inc.
- Murong Lang
- G11 - INFORMATION STORAGE
Information Patent Application
SCHEDULING OF READ OPERATIONS AND WRITE OPERATIONS BASED ON A DATA...
- Publication number 20240104030
- Publication date Mar 28, 2024
- Micron Technology, Inc.
- Wei WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING TRIM COMMANDS IN A MEMORY SUB-SYSTEM
- Publication number 20240103752
- Publication date Mar 28, 2024
- Micron Technology, Inc.
- Yueh-Hung Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC PARTITION COMMAND QUEUES FOR A MEMORY DEVICE
- Publication number 20240078048
- Publication date Mar 7, 2024
- Micron Technology, Inc.
- Juane Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT PERIODIC BACKEND REFRESH READS FOR REDUCING BIT ERROR RAT...
- Publication number 20240071462
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Tingjun Xie
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCING BIT ERROR RATE IN MEMORY DEVICES
- Publication number 20240069748
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Tingjun Xie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE-PASS PROGRAMMING OF MEMORY CELLS USING TEMPORARY PARITY GE...
- Publication number 20240045616
- Publication date Feb 8, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING POWER LOSS IN A MEMORY DEVICE
- Publication number 20240037033
- Publication date Feb 1, 2024
- Micron Technology, Inc.
- Huapeng G. Guan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFER ALLOCATION FOR REDUCING BLOCK TRANSIT PENALTY
- Publication number 20240028259
- Publication date Jan 25, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION
- Publication number 20240029815
- Publication date Jan 25, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Application
ENABLING STRIPE-BASED OPERATIONS FOR ERROR RECOVERY AT A MEMORY SUB...
- Publication number 20230409210
- Publication date Dec 21, 2023
- Micron Technology, Inc.
- Juane Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CELL VOLTAGE LEVEL SELECTION
- Publication number 20230395152
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Tingjun Xie
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS WITH READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE...
- Publication number 20230393758
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Murong Lang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS WITH READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE...
- Publication number 20230395162
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Murong Lang
- G11 - INFORMATION STORAGE
Information Patent Application
ENABLING MULTIPLE DATA CAPACITY MODES AT A MEMORY SUB-SYSTEM
- Publication number 20230359398
- Publication date Nov 9, 2023
- Micron Technology, Inc.
- Fangfang Zhu
- G06 - COMPUTING CALCULATING COUNTING

Jiangli Zhu

Person

Patents Grantslast 30 patents

Cryptographic key management

Open translation unit management using an adaptive read threshold

Concurrent command limiter for a memory system

Memory cell voltage level selection

Detect whether die or channel is defective to confirm temperature data

Write determination counter

Partition command queues for a memory device

Managing power loss in a memory device

Buffer allocation for reducing block transit penalty

Memory block programming using defectivity information

Selecting a write operation mode from multiple write operation modes

Double threshold controlled scheduling of memory access commands

Hardware based status collector acceleration engine for memory sub-...

Multiple-pass programming of memory cells using temporary parity ge...

Unified sequencer concurrency controller for a memory sub-system

Apparatus with read level management and methods for operating the...

Decreasing a quantity of queues to adjust a read throughput level f...

Managing the programming of an open translation unit

Managing an adjustable write-to-read delay based on cycle counts in...

Clock domain crossing queue

Reduce read command latency in partition command scheduling at a me...

Concurrent command limiter for a memory system

Consolidating write request in cache memory

Open translation unit management using an adaptive read threshold

Scheduling of read operations and write operations based on a data...

Maintaining data consistency in a memory sub-system that uses hybri...

Managing trim commands in a memory sub-system

Memory sub-system including an in-package sequencer to perform erro...

Management unit based media management operations in memory devices

Maintenance operations for memory devices

Patents Applicationslast 30 patents

RELIABILITY IMPROVEMENTS USING MEMORY DIE BINNING

PARTITION COMMAND QUEUES FOR A MEMORY DEVICE

BUFFER ALLOCATION FOR REDUCING BLOCK TRANSIT PENALTY

POWER-OFF MONITOR FOR RELAXED BLOCK RETIREMENT IN A MEMORY SUB-SYSTEM

HARDWARE BASED STATUS COLLECTOR ACCELERATION ENGINE FOR MEMORY SUB-...

MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION

PARTIALLY GOOD BLOCK HANDLING IN A MEMORY DEVICE

MULTIPLE-PASS PROGRAMMING OF MEMORY CELLS USING TEMPORARY PARITY GE...

APPARATUS WITH TIME-BASED READ LEVEL MANAGEMENT AND METHODS FOR OPE...

UNIFIED SEQUENCER CONCURRENCY CONTROLLER FOR A MEMORY SUB-SYSTEM

REMAPPING BAD BLOCKS IN A MEMORY SUB-SYSTEM

MANAGING THE PROGRAMMING OF AN OPEN TRANSLATION UNIT

REDUCE READ COMMAND LATENCY IN PARTITION COMMAND SCHEDULING AT A ME...

CONSOLIDATING WRITE REQUEST IN CACHE MEMORY

CONCURRENT COMMAND LIMITER FOR A MEMORY SYSTEM

OPEN TRANSLATION UNIT MANAGEMENT USING AN ADAPTIVE READ THRESHOLD

SCHEDULING OF READ OPERATIONS AND WRITE OPERATIONS BASED ON A DATA...

MANAGING TRIM COMMANDS IN A MEMORY SUB-SYSTEM

DYNAMIC PARTITION COMMAND QUEUES FOR A MEMORY DEVICE

EFFICIENT PERIODIC BACKEND REFRESH READS FOR REDUCING BIT ERROR RAT...

REDUCING BIT ERROR RATE IN MEMORY DEVICES

MULTIPLE-PASS PROGRAMMING OF MEMORY CELLS USING TEMPORARY PARITY GE...

MANAGING POWER LOSS IN A MEMORY DEVICE

BUFFER ALLOCATION FOR REDUCING BLOCK TRANSIT PENALTY

MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION

ENABLING STRIPE-BASED OPERATIONS FOR ERROR RECOVERY AT A MEMORY SUB...

MEMORY CELL VOLTAGE LEVEL SELECTION

APPARATUS WITH READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE...

APPARATUS WITH READ LEVEL MANAGEMENT AND METHODS FOR OPERATING THE...

ENABLING MULTIPLE DATA CAPACITY MODES AT A MEMORY SUB-SYSTEM