Jianlin Yu

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Cupertino, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
System on a chip (SOC) debug controllability
- Patent number 8,799,715
- Issue date Aug 5, 2014
- Apple Inc.
- Manu Gulati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory content protection during scan dumps and memory dumps
- Patent number 8,589,749
- Issue date Nov 19, 2013
- Apple Inc.
- Jianlin Yu
- G01 - MEASURING TESTING
Information Patent Grant
Secure register scan bypass
- Patent number 8,495,443
- Issue date Jul 23, 2013
- Apple Inc.
- Jianlin Yu
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit having secure access to test modes
- Patent number 8,120,377
- Issue date Feb 21, 2012
- Apple Inc.
- Jianlin Yu
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Apparatus and Method for Controlling Internal Test Controllers
- Publication number 20150046763
- Publication date Feb 12, 2015
- Apple Inc.
- Samy R. Makar
- G01 - MEASURING TESTING
Information Patent Application
System on a Chip (SOC) Debug Controllability
- Publication number 20130346800
- Publication date Dec 26, 2013
- Manu Gulati
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT HAVING SECURE ACCESS TO TEST MODES
- Publication number 20100333055
- Publication date Dec 30, 2010
- Jianlin Yu
- G06 - COMPUTING CALCULATING COUNTING