Jiann-Cherng Lan

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Single stage pulsed domino circuit for driving cascaded skewed stat...
- Patent number 6,833,735
- Issue date Dec 21, 2004
- Intel Corporation
- Sudarshan Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power precharge scheme for memory bit lines
- Patent number 6,631,093
- Issue date Oct 7, 2003
- Intel Corporation
- Sudarshan Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for low power memory bit line precharge
- Patent number 6,629,194
- Issue date Sep 30, 2003
- Intel Corporation
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-entry register cell
- Patent number 6,628,539
- Issue date Sep 30, 2003
- Intel Corporation
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power clock buffer with shared, precharge transistor
- Patent number 6,369,616
- Issue date Apr 9, 2002
- Intel Corporation
- Jiann-Cherng James Lan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reducing power consumption in a data storage device
- Patent number 6,341,099
- Issue date Jan 22, 2002
- Intel Corporation
- Sudarshan Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power clock buffer with shared, clocked transistor
- Patent number 6,127,850
- Issue date Oct 3, 2000
- Intel Corporation
- Jiann-Cherng James Lan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power clock buffer having a reduced, clocked, pull-down transistor
- Patent number 6,124,737
- Issue date Sep 26, 2000
- Intel Corporation
- Jiann-Cherng James Lan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power multiplexer with shared, clocked transistor
- Patent number 6,111,435
- Issue date Aug 29, 2000
- Intel Corporation
- Jiann-Cherng James Lan
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Single stage pulsed domino circuit for driving cascaded skewed stat...
- Publication number 20040124882
- Publication date Jul 1, 2004
- Intel Corporation
- Sudarshan Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW POWER PRECHARGE SCHEME FOR MEMORY BIT LINES
- Publication number 20030002382
- Publication date Jan 2, 2003
- Sudarshan Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for low power memory bit line precharge
- Publication number 20020184431
- Publication date Dec 5, 2002
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-entry register cell
- Publication number 20020181268
- Publication date Dec 5, 2002
- Sudarshan Kumar
- G06 - COMPUTING CALCULATING COUNTING

Jiann-Cherng Lan

Person

Patents Grantslast 30 patents

Single stage pulsed domino circuit for driving cascaded skewed stat...

Low power precharge scheme for memory bit lines

Method and apparatus for low power memory bit line precharge

Multi-entry register cell

Low power clock buffer with shared, precharge transistor

Reducing power consumption in a data storage device

Low power clock buffer with shared, clocked transistor

Low power clock buffer having a reduced, clocked, pull-down transistor

Low power multiplexer with shared, clocked transistor

Patents Applicationslast 30 patents

Single stage pulsed domino circuit for driving cascaded skewed stat...

LOW POWER PRECHARGE SCHEME FOR MEMORY BIT LINES

Method and apparatus for low power memory bit line precharge

Multi-entry register cell