Jiasheng Chen

Person

Orlando, FL, US

People

Patents Grantslast 30 patents

Information Patent Grant
Large integer multiplication enhancements for graphics environment
- Patent number 12,236,238
- Issue date Feb 25, 2025
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture for block sparse operations on a systolic array
- Patent number 12,198,222
- Issue date Jan 14, 2025
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual pipeline parallel systolic array
- Patent number 12,189,571
- Issue date Jan 7, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using sparsity metadata to reduce systolic array power consumption
- Patent number 12,190,158
- Issue date Jan 7, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Random sparsity handling in a systolic array
- Patent number 12,086,205
- Issue date Sep 10, 2024
- Intel Corporation
- Chunhui Mei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stream processor with low power parallel matrix multiply pipeline
- Patent number 12,067,401
- Issue date Aug 20, 2024
- Advanced Micro Devices, Inc.
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Packed 16 bits instruction pipeline
- Patent number 11,880,683
- Issue date Jan 23, 2024
- Advanced Micro Devices, Inc.
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dot product operations on sparse matrix elements
- Patent number 11,842,423
- Issue date Dec 12, 2023
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arithmetic logic unit register sequencing
- Patent number 11,789,732
- Issue date Oct 17, 2023
- Advanced Micro Devices, Inc.
- Bin He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing unit with mixed precision operations
- Patent number 11,768,664
- Issue date Sep 26, 2023
- Advanced Micro Devices, Inc.
- Bin He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Matrix multiplication unit with flexible precision operations
- Patent number 11,762,658
- Issue date Sep 19, 2023
- Advanced Micro Devices, Inc.
- Bin He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dedicated vector sub-processor system
- Patent number 11,630,667
- Issue date Apr 18, 2023
- Advanced Micro Devices, Inc.
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power and low latency GPU coprocessor for persistent computing
- Patent number 11,625,807
- Issue date Apr 11, 2023
- Advanced Micro Devices, Inc.
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipeline including separate hardware data paths for different instr...
- Patent number 11,494,192
- Issue date Nov 8, 2022
- Advanced Micro Devices, Inc.
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pairing SIMD lanes to perform double precision operations
- Patent number 11,409,536
- Issue date Aug 9, 2022
- Advanced Micro Devices, Inc.
- Bin He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid matrix multiplication pipeline
- Patent number 11,347,827
- Issue date May 31, 2022
- Advanced Micro Devices, Inc.
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arithemetic logic unit register sequencing
- Patent number 11,237,827
- Issue date Feb 1, 2022
- Advanced Micro Devices, Inc.
- Bin He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stream processor with decoupled crossbar for cross lane operations
- Patent number 10,970,081
- Issue date Apr 6, 2021
- Advanced Micro Devices, Inc.
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power and low latency GPU coprocessor for persistent computing
- Patent number 10,929,944
- Issue date Feb 23, 2021
- Advanced Micro Devices, Inc.
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor support for bypassing vector source operands
- Patent number 10,817,302
- Issue date Oct 27, 2020
- Advanced Micro Devices, Inc.
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipeline including separate hardware data paths for different instr...
- Patent number 10,656,951
- Issue date May 19, 2020
- Advanced Micro Devices, Inc.
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Extreme-bandwidth scalable performance-per-watt GPU architecture
- Patent number 10,509,596
- Issue date Dec 17, 2019
- Advanced Micro Devices, Inc.
- Dmitri Yudanov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and processing apparatus for gating redundant threads
- Patent number 10,360,177
- Issue date Jul 23, 2019
- ATI Technologies ULC
- Syed Zohaib M. Gilani
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
- Publication number 20250166114
- Publication date May 22, 2025
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL PIPELINE PARALLEL SYSTOLIC ARRAY
- Publication number 20250117359
- Publication date Apr 10, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONVERSION OPERATIONS AND SPECIAL VALUE USE CASES SUPPORTING 8-BIT...
- Publication number 20250110733
- Publication date Apr 3, 2025
- Intel Corporation
- Jorge Eduardo Parra Osorio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING 8-BIT FLOATING POINT FORMAT FOR PARALLEL COMPUTING AND S...
- Publication number 20250110741
- Publication date Apr 3, 2025
- Intel Corporation
- Jorge Eduardo Parra Osorio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
- Publication number 20250104180
- Publication date Mar 27, 2025
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNBLOCKING THE INTEGER PIPELINE DURING MATH PIPELINE PHASES IN A GR...
- Publication number 20250085969
- Publication date Mar 13, 2025
- Intel Corporation
- Shuai Mu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED REGISTER FILE CACHE TO REDUCE L1 BANDWIDTH REQUIREMENTS
- Publication number 20250068473
- Publication date Feb 27, 2025
- Intel Corporation
- Jorge Eduardo Parra Osorio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION ENCODING TO IMPLEMENT INCREASED REGISTER CAPACITY PER T...
- Publication number 20250068423
- Publication date Feb 27, 2025
- Intel Corporation
- Jorge Eduardo Parra Osorio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RANDOM SPARSITY HANDLING IN A SYSTOLIC ARRAY
- Publication number 20250053613
- Publication date Feb 13, 2025
- Intel Corporation
- Chunhui Mei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
32-BIT CHANNEL-ALIGNED INTEGER MULTIPLICATION VIA MULTIPLE MULTIPLI...
- Publication number 20250037347
- Publication date Jan 30, 2025
- Intel Corporation
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLOATING-POINT CONVERSION VIA AN INTEGER UNIT
- Publication number 20250036361
- Publication date Jan 30, 2025
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AVOIDING THE USE OF A RESULT CROSSBAR WHEN DOWN CONVERTING TO PACKE...
- Publication number 20250036412
- Publication date Jan 30, 2025
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE AND CONFIGURABLE CLUSTERED SYSTOLIC ARRAY
- Publication number 20240220448
- Publication date Jul 4, 2024
- Intel Corporation
- Chunhui Mei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MATRIX TRANSPOSITION IN MATRIX MULTIPLICATION ARRAY CIRCUITRY
- Publication number 20240168723
- Publication date May 23, 2024
- Intel Corporation
- Jorge Eduardo Parra Osorio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENHANCEMENTS FOR ACCUMULATOR USAGE AND INSTRUCTION FORWARDING IN MA...
- Publication number 20240169021
- Publication date May 23, 2024
- Intel Corporation
- Jorge Eduardo Parra Osorio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING AND LOAD BALANCING MULTIPLE DOUBLE PRECISION PIPELINES I...
- Publication number 20240168764
- Publication date May 23, 2024
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREASING PROCESSING RESOURCES IN PROCESSING CORES OF A GRAPHICS E...
- Publication number 20240160478
- Publication date May 16, 2024
- Intel Corporation
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY
- Publication number 20240161227
- Publication date May 16, 2024
- Intel Corporation
- Abhishek Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MATRIX MULTIPLICATION UNIT WITH FLEXIBLE PRECISION OPERATIONS
- Publication number 20240111530
- Publication date Apr 4, 2024
- ADVANCED MICRO DEVICES, INC.
- Bin HE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE PRECISION SUPPORT FOR SYSTOLIC PIPELINE IN A GRAPHICS ENVIRO...
- Publication number 20240111825
- Publication date Apr 4, 2024
- Intel Corporation
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ENHANCEMENTS FOR DOUBLE PRECISION SYSTOLIC SUPPORT
- Publication number 20240111826
- Publication date Apr 4, 2024
- Intel Corporation
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING VECTOR MULTIPLY ADD WITH DOUBLE ACCUMULATOR ACCESS IN A...
- Publication number 20240103810
- Publication date Mar 28, 2024
- Intel Corporation
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMMEDIATE OFFSET OF LOAD STORE AND ATOMIC INSTRUCTIONS
- Publication number 20230090973
- Publication date Mar 23, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EMULATION OF FLOATING POINT CALCULATION
- Publication number 20230086275
- Publication date Mar 23, 2023
- Intel Corporation
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING SPARSITY METADATA TO REDUCE SYSTOLIC ARRAY POWER CONSUMPTION
- Publication number 20220413924
- Publication date Dec 29, 2022
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL PIPELINE PARALLEL SYSTOLIC ARRAY
- Publication number 20220414054
- Publication date Dec 29, 2022
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LARGE INTEGER MULTIPLICATION ENHANCEMENTS FOR GRAPHICS ENVIRONMENT
- Publication number 20220413848
- Publication date Dec 29, 2022
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RANDOM SPARSITY HANDLING IN A SYSTOLIC ARRAY
- Publication number 20220309124
- Publication date Sep 29, 2022
- Intel Corporation
- Chunhui Mei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARITHMETIC LOGIC UNIT REGISTER SEQUENCING
- Publication number 20220171621
- Publication date Jun 2, 2022
- ADVANCED MICRO DEVICES, INC.
- Bin HE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW POWER AND LOW LATENCY GPU COPROCESSOR FOR PERSISTENT COMPUTING
- Publication number 20210201439
- Publication date Jul 1, 2021
- ADVANCED MICRO DEVICES, INC.
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING

Jiasheng Chen

Person

Patents Grantslast 30 patents

Large integer multiplication enhancements for graphics environment

Architecture for block sparse operations on a systolic array

Dual pipeline parallel systolic array

Using sparsity metadata to reduce systolic array power consumption

Random sparsity handling in a systolic array

Stream processor with low power parallel matrix multiply pipeline

Packed 16 bits instruction pipeline

Dot product operations on sparse matrix elements

Arithmetic logic unit register sequencing

Processing unit with mixed precision operations

Matrix multiplication unit with flexible precision operations

Dedicated vector sub-processor system

Low power and low latency GPU coprocessor for persistent computing

Pipeline including separate hardware data paths for different instr...

Pairing SIMD lanes to perform double precision operations

Hybrid matrix multiplication pipeline

Arithemetic logic unit register sequencing

Stream processor with decoupled crossbar for cross lane operations

Low power and low latency GPU coprocessor for persistent computing

Processor support for bypassing vector source operands

Pipeline including separate hardware data paths for different instr...

Extreme-bandwidth scalable performance-per-watt GPU architecture

Method and processing apparatus for gating redundant threads

Patents Applicationslast 30 patents

ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY

DUAL PIPELINE PARALLEL SYSTOLIC ARRAY

CONVERSION OPERATIONS AND SPECIAL VALUE USE CASES SUPPORTING 8-BIT...

SUPPORTING 8-BIT FLOATING POINT FORMAT FOR PARALLEL COMPUTING AND S...

ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY

UNBLOCKING THE INTEGER PIPELINE DURING MATH PIPELINE PHASES IN A GR...

DISTRIBUTED REGISTER FILE CACHE TO REDUCE L1 BANDWIDTH REQUIREMENTS

INSTRUCTION ENCODING TO IMPLEMENT INCREASED REGISTER CAPACITY PER T...

RANDOM SPARSITY HANDLING IN A SYSTOLIC ARRAY

32-BIT CHANNEL-ALIGNED INTEGER MULTIPLICATION VIA MULTIPLE MULTIPLI...

FLOATING-POINT CONVERSION VIA AN INTEGER UNIT

AVOIDING THE USE OF A RESULT CROSSBAR WHEN DOWN CONVERTING TO PACKE...

SCALABLE AND CONFIGURABLE CLUSTERED SYSTOLIC ARRAY

MATRIX TRANSPOSITION IN MATRIX MULTIPLICATION ARRAY CIRCUITRY

ENHANCEMENTS FOR ACCUMULATOR USAGE AND INSTRUCTION FORWARDING IN MA...

SUPPORTING AND LOAD BALANCING MULTIPLE DOUBLE PRECISION PIPELINES I...

INCREASING PROCESSING RESOURCES IN PROCESSING CORES OF A GRAPHICS E...

ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY

MATRIX MULTIPLICATION UNIT WITH FLEXIBLE PRECISION OPERATIONS

SINGLE PRECISION SUPPORT FOR SYSTOLIC PIPELINE IN A GRAPHICS ENVIRO...

HARDWARE ENHANCEMENTS FOR DOUBLE PRECISION SYSTOLIC SUPPORT

SUPPORTING VECTOR MULTIPLY ADD WITH DOUBLE ACCUMULATOR ACCESS IN A...

IMMEDIATE OFFSET OF LOAD STORE AND ATOMIC INSTRUCTIONS

EMULATION OF FLOATING POINT CALCULATION

USING SPARSITY METADATA TO REDUCE SYSTOLIC ARRAY POWER CONSUMPTION

DUAL PIPELINE PARALLEL SYSTOLIC ARRAY

LARGE INTEGER MULTIPLICATION ENHANCEMENTS FOR GRAPHICS ENVIRONMENT

RANDOM SPARSITY HANDLING IN A SYSTOLIC ARRAY

ARITHMETIC LOGIC UNIT REGISTER SEQUENCING

LOW POWER AND LOW LATENCY GPU COPROCESSOR FOR PERSISTENT COMPUTING