Jiawen Zhang

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Irvine, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Integrated transimpedance amplifier with a digital signal processor...
- Patent number 11,722,109
- Issue date Aug 8, 2023
- Avago Technologies International Sales Pte. Limited
- Jiawen Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock skew suppression for time-interleaved clocks
- Patent number 10,277,210
- Issue date Apr 30, 2019
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Hyo Gyuem Rhew
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiplexer circuit for a digital to analog converter
- Patent number 10,069,508
- Issue date Sep 4, 2018
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Jiawen Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-segmented all logic DAC
- Patent number 10,014,877
- Issue date Jul 3, 2018
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Adesh Garg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Time-interleaved high-speed digital-to-analog converter (DAC) archi...
- Patent number 9,685,969
- Issue date Jun 20, 2017
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Adesh Garg
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED TRANSIMPEDANCE AMPLIFIER WITH A DIGITAL SIGNAL PROCESSOR...
- Publication number 20240154591
- Publication date May 9, 2024
- Avago Technologies International Sales Pte. Limited
- Jiawen Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK SKEW SUPPRESSION FOR TIME-INTERLEAVED CLOCKS
- Publication number 20190131958
- Publication date May 2, 2019
- Avago Technologies International Sales Pte. Limited
- Hyo Gyuem RHEW
- H03 - BASIC ELECTRONIC CIRCUITRY