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Jie Chen

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  • Saratoga, CA, US
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Patents Grantslast 30 patents

  • Information Patent Grant

    Reduced pin full feature load switch
    • Patent number 9,312,836
    • Issue date Apr 12, 2016
    • Silego Technology, Inc.
    • John Othniel McDonald
    • H03 - BASIC ELECTRONIC CIRCUITRY
  • Information Patent Grant

    Reduced pin full feature load switch
    • Patent number 9,065,435
    • Issue date Jun 23, 2015
    • Silego Technology, Inc.
    • John Othniel McDonald
    • H03 - BASIC ELECTRONIC CIRCUITRY
  • Information Patent Grant

    Reduced power output buffer
    • Patent number 8,138,785
    • Issue date Mar 20, 2012
    • Silego Technology, Inc.
    • Jie Chen
    • H03 - BASIC ELECTRONIC CIRCUITRY
  • Information Patent Grant

    Reduced power output buffer
    • Patent number 7,612,580
    • Issue date Nov 3, 2009
    • Silego Technology, Inc.
    • Jie Chen
    • H03 - BASIC ELECTRONIC CIRCUITRY
  • Information Patent Grant

    Reduced power output buffer
    • Patent number 7,358,772
    • Issue date Apr 15, 2008
    • Silego Technology, Inc.
    • Jie Chen
    • H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

  • Information Patent Application

    Reduced power output buffer
    • Publication number 20100148817
    • Publication date Jun 17, 2010
    • Silego Technology, Inc.
    • Jie Chen
    • H03 - BASIC ELECTRONIC CIRCUITRY
  • Information Patent Application

    Reduced power output buffer
    • Publication number 20080204070
    • Publication date Aug 28, 2008
    • Silego Technology, Inc.
    • Jie Chen
    • H03 - BASIC ELECTRONIC CIRCUITRY