Jim Valerio

Person

North Plains, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Base plus offset addressing for load/store messages
- Patent number 12,333,310
- Issue date Jun 17, 2025
- Intel Corporation
- John Wiegert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,182,062
- Issue date Dec 31, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Barrier state save and restore for preemption in a graphics environ...
- Patent number 12,164,952
- Issue date Dec 10, 2024
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction prefetch based on thread dispatch commands
- Patent number 12,124,852
- Issue date Oct 22, 2024
- Intel Corporation
- James Valerio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,099,461
- Issue date Sep 24, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Base plus offset addressing for load/store messages
- Patent number 12,014,183
- Issue date Jun 18, 2024
- Intel Corporation
- John Wiegert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread scheduling over compute blocks for power optimization
- Patent number 11,995,737
- Issue date May 28, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical thread scheduling based on multiple barriers
- Patent number 11,977,895
- Issue date May 7, 2024
- Intel Corporation
- Sabareesh Ganapathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction prefetch based on thread dispatch commands
- Patent number 11,762,662
- Issue date Sep 19, 2023
- Intel Corporation
- James Valerio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic load balancing of compute assets among different compute co...
- Patent number 11,726,826
- Issue date Aug 15, 2023
- Intel Corporation
- James Valerio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register spill/fill using shared local memory space
- Patent number 11,508,338
- Issue date Nov 22, 2022
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-based software barriers
- Patent number 11,494,232
- Issue date Nov 8, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Workload scheduling and distribution on a distributed graphics device
- Patent number 11,481,864
- Issue date Oct 25, 2022
- Intel Corporation
- Balaji Vembu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coarse grain coherency
- Patent number 11,436,695
- Issue date Sep 6, 2022
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple independent synchonization named barrier within a thread g...
- Patent number 11,409,579
- Issue date Aug 9, 2022
- Intel Corporation
- James Valerio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intelligent graphics dispatching mechanism
- Patent number 11,354,768
- Issue date Jun 7, 2022
- Intel Corporation
- Balaji Vembu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnected systems fence mechanism
- Patent number 11,321,262
- Issue date May 3, 2022
- Intel Corporation
- Hema Chand Nalluri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Partial write management in a multi-tiled compute engine
- Patent number 11,301,384
- Issue date Apr 12, 2022
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Range based flushing mechanism
- Patent number 11,288,191
- Issue date Mar 29, 2022
- Intel Corporation
- Hema Chand Nalluri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Replacement policies for a hybrid hierarchical cache
- Patent number 11,263,152
- Issue date Mar 1, 2022
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread scheduling over compute blocks for power optimization
- Patent number 11,227,360
- Issue date Jan 18, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for improved cache utilization and efficiency...
- Patent number 11,194,722
- Issue date Dec 7, 2021
- Intel Corporation
- Bharath Narasimha Swamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microcontroller-based flexible thread scheduling launching in compu...
- Patent number 11,175,949
- Issue date Nov 16, 2021
- Intel Corporation
- Kiran C. Veernapu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Switching crossbar for graphics pipeline
- Patent number 11,176,083
- Issue date Nov 16, 2021
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction prefetch based on thread dispatch commands
- Patent number 11,157,283
- Issue date Oct 26, 2021
- Intel Corporation
- James Valerio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic load balancing of compute assets among different compute co...
- Patent number 11,074,109
- Issue date Jul 27, 2021
- Intel Corporation
- James Valerio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Workload scheduling and distribution on a distributed graphics device
- Patent number 10,997,686
- Issue date May 4, 2021
- Intel Corporation
- Balaji Vembu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coarse grain coherency
- Patent number 10,949,945
- Issue date Mar 16, 2021
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimizing memory address compression
- Patent number 10,909,037
- Issue date Feb 2, 2021
- INTEL CORPOR ATION
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Independent and separate entity-based cache
- Patent number 10,884,932
- Issue date Jan 5, 2021
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
BINDLESS THREAD DISPATCH MID-THREAD PREEMPTION ON A GRAPHICS PROCESSOR
- Publication number 20250231769
- Publication date Jul 17, 2025
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR MID-THREAD PREEMPTION
- Publication number 20250232511
- Publication date Jul 17, 2025
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE REGISTER ALLOCATION SIZES FOR GPU HARDWARE THREADS
- Publication number 20250147762
- Publication date May 8, 2025
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BARRIER STATE SAVE AND RESTORE FOR PREEMPTION IN A GRAPHICS ENVIRON...
- Publication number 20250130848
- Publication date Apr 24, 2025
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250117356
- Publication date Apr 10, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION PREFETCH BASED ON THREAD DISPATCH COMMANDS
- Publication number 20250077232
- Publication date Mar 6, 2025
- Intel Corporation
- JAMES VALERIO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED REGISTER FILE CACHE TO REDUCE L1 BANDWIDTH REQUIREMENTS
- Publication number 20250068473
- Publication date Feb 27, 2025
- Intel Corporation
- Jorge Eduardo Parra Osorio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION ENCODING TO IMPLEMENT INCREASED REGISTER CAPACITY PER T...
- Publication number 20250068423
- Publication date Feb 27, 2025
- Intel Corporation
- Jorge Eduardo Parra Osorio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
32-BIT CHANNEL-ALIGNED INTEGER MULTIPLICATION VIA MULTIPLE MULTIPLI...
- Publication number 20250037347
- Publication date Jan 30, 2025
- Intel Corporation
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLOATING-POINT CONVERSION VIA AN INTEGER UNIT
- Publication number 20250036361
- Publication date Jan 30, 2025
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AVOIDING THE USE OF A RESULT CROSSBAR WHEN DOWN CONVERTING TO PACKE...
- Publication number 20250036412
- Publication date Jan 30, 2025
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250004981
- Publication date Jan 2, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COARSE AND FINE FILTERING FOR GPU HARDWARE-BASED PERFORMANCE MONITO...
- Publication number 20240420274
- Publication date Dec 19, 2024
- Intel Corporation
- Prashant D. Chaudhari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD SCHEDULING OVER COMPUTE BLOCKS FOR POWER OPTIMIZATION
- Publication number 20240362741
- Publication date Oct 31, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES
- Publication number 20240330001
- Publication date Oct 3, 2024
- Intel Corporation
- John Wiegert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONIZATION FOR DATA MULTICAST IN COMPUTE CORE CLUSTERS
- Publication number 20240220335
- Publication date Jul 4, 2024
- Intel Corporation
- Chunhui Mei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA MULTICAST IN COMPUTE CORE CLUSTERS
- Publication number 20240220254
- Publication date Jul 4, 2024
- Intel Corporation
- Chunhui Mei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONIZATION UTILIZING LOCAL TEAM BARRIERS FOR THREAD TEAM PROCE...
- Publication number 20240111609
- Publication date Apr 4, 2024
- Intel Corporation
- Biju George
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES
- Publication number 20240095038
- Publication date Mar 21, 2024
- Intel Corporation
- John Wiegert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU...
- Publication number 20240086357
- Publication date Mar 14, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OFFSET SCALING IN LOAD/STORE MESSAGES
- Publication number 20240086064
- Publication date Mar 14, 2024
- Intel Corporation
- John Wiegert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONCURRENT COMPUTE CONTEXT
- Publication number 20240054595
- Publication date Feb 15, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Method for Concurrent Performance Monitoring per Comp...
- Publication number 20240045725
- Publication date Feb 8, 2024
- Prashant CHAUDHARI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION PREFETCH BASED ON THREAD DISPATCH COMMANDS
- Publication number 20230401064
- Publication date Dec 14, 2023
- Intel Corporation
- JAMES VALERIO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC LOAD BALANCING OF COMPUTE ASSETS AMONG DIFFERENT COMPUTE CO...
- Publication number 20230359499
- Publication date Nov 9, 2023
- Intel Corporation
- James VALERIO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FORWARD PROGRESS GUARANTEE USING SINGLE-LEVEL SYNCHRONIZATION AT IN...
- Publication number 20230153176
- Publication date May 18, 2023
- Intel Corporation
- Chunhui Mei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNIFIED SUBMIT PORT FOR GRAPHICS PROCESSING
- Publication number 20230094002
- Publication date Mar 30, 2023
- Intel Corporation
- Hema Chand Nalluri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMMEDIATE OFFSET OF LOAD STORE AND ATOMIC INSTRUCTIONS
- Publication number 20230090973
- Publication date Mar 23, 2023
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WORKLOAD SCHEDULING AND DISTRIBUTION ON A DISTRIBUTED GRAPHICS DEVICE
- Publication number 20230039853
- Publication date Feb 9, 2023
- Intel Corporation
- Balaji Vembu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BARRIER STATE SAVE AND RESTORE FOR PREEMPTION IN A GRAPHICS ENVIRON...
- Publication number 20220413899
- Publication date Dec 29, 2022
- Intel Corporation
- Vasanth Ranganathan
- G06 - COMPUTING CALCULATING COUNTING

Jim Valerio

Person

Patents Grantslast 30 patents

Base plus offset addressing for load/store messages

Multi-tile memory management

Barrier state save and restore for preemption in a graphics environ...

Instruction prefetch based on thread dispatch commands

Multi-tile memory management

Base plus offset addressing for load/store messages

Thread scheduling over compute blocks for power optimization

Hierarchical thread scheduling based on multiple barriers

Instruction prefetch based on thread dispatch commands

Dynamic load balancing of compute assets among different compute co...

Register spill/fill using shared local memory space

Memory-based software barriers

Workload scheduling and distribution on a distributed graphics device

Coarse grain coherency

Multiple independent synchonization named barrier within a thread g...

Intelligent graphics dispatching mechanism

Interconnected systems fence mechanism

Partial write management in a multi-tiled compute engine

Range based flushing mechanism

Replacement policies for a hybrid hierarchical cache

Thread scheduling over compute blocks for power optimization

Apparatus and method for improved cache utilization and efficiency...

Microcontroller-based flexible thread scheduling launching in compu...

Switching crossbar for graphics pipeline

Instruction prefetch based on thread dispatch commands

Dynamic load balancing of compute assets among different compute co...

Workload scheduling and distribution on a distributed graphics device

Coarse grain coherency

Optimizing memory address compression

Independent and separate entity-based cache

Patents Applicationslast 30 patents

BINDLESS THREAD DISPATCH MID-THREAD PREEMPTION ON A GRAPHICS PROCESSOR

GRAPHICS PROCESSOR MID-THREAD PREEMPTION

MULTIPLE REGISTER ALLOCATION SIZES FOR GPU HARDWARE THREADS

BARRIER STATE SAVE AND RESTORE FOR PREEMPTION IN A GRAPHICS ENVIRON...

MULTI-TILE MEMORY MANAGEMENT

INSTRUCTION PREFETCH BASED ON THREAD DISPATCH COMMANDS

DISTRIBUTED REGISTER FILE CACHE TO REDUCE L1 BANDWIDTH REQUIREMENTS

INSTRUCTION ENCODING TO IMPLEMENT INCREASED REGISTER CAPACITY PER T...

32-BIT CHANNEL-ALIGNED INTEGER MULTIPLICATION VIA MULTIPLE MULTIPLI...

FLOATING-POINT CONVERSION VIA AN INTEGER UNIT

AVOIDING THE USE OF A RESULT CROSSBAR WHEN DOWN CONVERTING TO PACKE...

MULTI-TILE MEMORY MANAGEMENT

COARSE AND FINE FILTERING FOR GPU HARDWARE-BASED PERFORMANCE MONITO...

THREAD SCHEDULING OVER COMPUTE BLOCKS FOR POWER OPTIMIZATION

BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES

SYNCHRONIZATION FOR DATA MULTICAST IN COMPUTE CORE CLUSTERS

DATA MULTICAST IN COMPUTE CORE CLUSTERS

SYNCHRONIZATION UTILIZING LOCAL TEAM BARRIERS FOR THREAD TEAM PROCE...

BASE PLUS OFFSET ADDRESSING FOR LOAD/STORE MESSAGES

SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU...

OFFSET SCALING IN LOAD/STORE MESSAGES

CONCURRENT COMPUTE CONTEXT

Apparatus and Method for Concurrent Performance Monitoring per Comp...

INSTRUCTION PREFETCH BASED ON THREAD DISPATCH COMMANDS

DYNAMIC LOAD BALANCING OF COMPUTE ASSETS AMONG DIFFERENT COMPUTE CO...

FORWARD PROGRESS GUARANTEE USING SINGLE-LEVEL SYNCHRONIZATION AT IN...

UNIFIED SUBMIT PORT FOR GRAPHICS PROCESSING

IMMEDIATE OFFSET OF LOAD STORE AND ATOMIC INSTRUCTIONS

WORKLOAD SCHEDULING AND DISTRIBUTION ON A DISTRIBUTED GRAPHICS DEVICE

BARRIER STATE SAVE AND RESTORE FOR PREEMPTION IN A GRAPHICS ENVIRON...