Jimmy Hsu

Person

Taipei Hsien, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Testing circuit and related method of injecting a time jitter
- Patent number 7,516,374
- Issue date Apr 7, 2009
- VIA Technologies Inc.
- Jimmy Hsu
- G01 - MEASURING TESTING
Information Patent Grant
Multi-conducting through hole structure
- Patent number 7,470,864
- Issue date Dec 30, 2008
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Signal transmission structure and circuit substrate thereof
- Patent number 7,378,601
- Issue date May 27, 2008
- VIA Technologies, Inc.
- Jimmy Hsu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Voltage reference signal circuit layout inside multi-layered substrate
- Patent number 7,356,782
- Issue date Apr 8, 2008
- VIA Technologies, Inc.
- Jimmy Hsu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method for analyzing power distribution system and related techniques
- Patent number 7,269,521
- Issue date Sep 11, 2007
- VIA Technologies Inc.
- Jimmy Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal transmission structure having plural reference planes with n...
- Patent number 7,202,758
- Issue date Apr 10, 2007
- VIA Technologies, Inc.
- Jimmy Hsu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Signal transmission structure having salients aligned with non-refe...
- Patent number 7,106,145
- Issue date Sep 12, 2006
- VIA Technologies, Inc.
- Jimmy Hsu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Chip package
- Patent number 7,091,608
- Issue date Aug 15, 2006
- Chunghwa Picture Tubes, Ltd.
- Jimmy Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Signal transmission structure having a non-reference region for mat...
- Patent number 7,064,627
- Issue date Jun 20, 2006
- VIA Technologies, Inc.
- Jimmy Hsu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Surrounding structure for a probe card
- Patent number 7,053,638
- Issue date May 30, 2006
- VIA Technologies Inc.
- Chi-Hsing Hsu
- G01 - MEASURING TESTING
Information Patent Grant
Signal transmission structure
- Patent number 7,002,432
- Issue date Feb 21, 2006
- VIA Technologies, Inc.
- Jimmy Hsu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Bonding pad design for impedance matching improvement
- Patent number 6,919,621
- Issue date Jul 19, 2005
- VIA Technologies, Inc.
- Jimmy Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transformer former between two layout layers
- Patent number 6,914,509
- Issue date Jul 5, 2005
- VIA Technologies Inc.
- Jay Yu
- G11 - INFORMATION STORAGE
Information Patent Grant
Chip package structure
- Patent number 6,876,084
- Issue date Apr 5, 2005
- VIA Technologies, Inc.
- Jimmy Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip-chip package substrate
- Patent number 6,774,498
- Issue date Aug 10, 2004
- VIA Technologies, Inc.
- Chi-Hsing Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip-chip package substrate
- Patent number 6,740,965
- Issue date May 25, 2004
- VIA Technologies, Inc.
- Chi-Hsing Hsu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
Testing Circuit and Related Method of Injecting a Time Jitter
- Publication number 20070061658
- Publication date Mar 15, 2007
- Jimmy Hsu
- G01 - MEASURING TESTING
Information Patent Application
Method for Analyzing Power Distribution System and Related Techniques
- Publication number 20070040535
- Publication date Feb 22, 2007
- Jimmy Hsu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Signal transmission structure and circuit substrate thereof
- Publication number 20060108143
- Publication date May 25, 2006
- Jimmy Hsu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Signal transmission structure
- Publication number 20060071739
- Publication date Apr 6, 2006
- Jimmy Hsu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Chip package
- Publication number 20060065959
- Publication date Mar 30, 2006
- Jimmy Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi-conducting through hole structure
- Publication number 20060012030
- Publication date Jan 19, 2006
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Surrounding structure for a probe card
- Publication number 20050253604
- Publication date Nov 17, 2005
- Via Technologies, Inc.
- Chi-Hsing Hsu
- G01 - MEASURING TESTING
Information Patent Application
VOLTAGE REFERENCE SIGNAL CIRCUIT LAYOUT INSIDE MULTI-LAYERED SUBSTRATE
- Publication number 20050235233
- Publication date Oct 20, 2005
- Jimmy Hsu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Signal transmission structure
- Publication number 20050083152
- Publication date Apr 21, 2005
- Jimmy Hsu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Signal transmission structure
- Publication number 20050083148
- Publication date Apr 21, 2005
- Jimmy Hsu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Bonding pad design for impedance matching improvement
- Publication number 20050051897
- Publication date Mar 10, 2005
- Via Technologies, Inc.
- Jimmy Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Signal transmission structure
- Publication number 20050017827
- Publication date Jan 27, 2005
- Jimmy Hsu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
INDUCTOR FORMED BETWEEN TWO LAYOUT LAYERS
- Publication number 20040263308
- Publication date Dec 30, 2004
- Jay Yu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Structure of multi-tier wire bonding for high frequency integrated...
- Publication number 20040227226
- Publication date Nov 18, 2004
- Via Technologies, Inc.
- Jimmy Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Transformer formed between two layout layers
- Publication number 20040196132
- Publication date Oct 7, 2004
- Jay Yu
- G11 - INFORMATION STORAGE
Information Patent Application
Chip package structure
- Publication number 20040042188
- Publication date Mar 4, 2004
- VIA TECHNOLOGIES, INC.
- Jimmy Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flip-chip package substrate
- Publication number 20030234118
- Publication date Dec 25, 2003
- Chi-Hsing Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flip-chip package substrate
- Publication number 20030201122
- Publication date Oct 30, 2003
- Chi-Hsing Hsu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Voltage reference circuit layout inside multi-layered substrate
- Publication number 20030149942
- Publication date Aug 7, 2003
- Jimmy Hsu
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Person

Patents Grantslast 30 patents

Testing circuit and related method of injecting a time jitter

Multi-conducting through hole structure

Signal transmission structure and circuit substrate thereof

Voltage reference signal circuit layout inside multi-layered substrate

Method for analyzing power distribution system and related techniques

Signal transmission structure having plural reference planes with n...

Signal transmission structure having salients aligned with non-refe...

Chip package

Signal transmission structure having a non-reference region for mat...

Surrounding structure for a probe card

Signal transmission structure

Bonding pad design for impedance matching improvement

Transformer former between two layout layers

Chip package structure

Flip-chip package substrate

Flip-chip package substrate

Patents Applicationslast 30 patents

Testing Circuit and Related Method of Injecting a Time Jitter

Method for Analyzing Power Distribution System and Related Techniques

Signal transmission structure and circuit substrate thereof

Signal transmission structure

Chip package

Multi-conducting through hole structure

Surrounding structure for a probe card

VOLTAGE REFERENCE SIGNAL CIRCUIT LAYOUT INSIDE MULTI-LAYERED SUBSTRATE

Signal transmission structure

Signal transmission structure

Bonding pad design for impedance matching improvement

Signal transmission structure

INDUCTOR FORMED BETWEEN TWO LAYOUT LAYERS

Structure of multi-tier wire bonding for high frequency integrated...

Transformer formed between two layout layers

Chip package structure

Flip-chip package substrate

Flip-chip package substrate

Voltage reference circuit layout inside multi-layered substrate