Jin Ping Liu

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Reliable non-volatile memory device
- Patent number 10,475,891
- Issue date Nov 12, 2019
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Jin Qiu Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained channel transistor structure and method
- Patent number 8,754,447
- Issue date Jun 17, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Jin Ping Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained channel transistor structure and method
- Patent number 7,776,699
- Issue date Aug 17, 2010
- Chartered Semiconductor Manufacturing, Ltd.
- Jin Ping Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a relaxed semiconductor buffer layer on a substra...
- Patent number 7,166,522
- Issue date Jan 23, 2007
- Chartered Semiconductor Manufacturing Ltd.
- Jin Ping Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon-germanium virtual substrate and method of fabricating the same
- Patent number 7,064,037
- Issue date Jun 20, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Jin Ping Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a relaxed semiconductor buffer layer on a substra...
- Patent number 6,995,078
- Issue date Feb 7, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Jin Ping Liu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
RELIABLE NON-VOLATILE MEMORY DEVICE
- Publication number 20180102414
- Publication date Apr 12, 2018
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Jin Qiu LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED CHANNEL TRANSISTOR STRUCTURE AND METHOD
- Publication number 20100308374
- Publication date Dec 9, 2010
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Jin Ping LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS-ENGINEERED LAYERS
- Publication number 20100109045
- Publication date May 6, 2010
- Chartered Semiconductor Manufacturing LTD.
- Jin Ping Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED CHANNEL TRANSISTOR STRUCTURE AND METHOD
- Publication number 20090194788
- Publication date Aug 6, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Jin Ping LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONS
- Publication number 20090146181
- Publication date Jun 11, 2009
- Chartered Semiconductor Manufacturing LTD.
- Chung Woh Lai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a relaxed semiconductor buffer layer on a substra...
- Publication number 20050164436
- Publication date Jul 28, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Jin Ping Liu
- C30 - CRYSTAL GROWTH
Information Patent Application
Method of forming a relaxed semiconductor buffer layer on a substra...
- Publication number 20050164473
- Publication date Jul 28, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Jin Ping Liu
- C30 - CRYSTAL GROWTH
Information Patent Application
Silicon - germanium virtual substrate and method of fabricating the...
- Publication number 20050153495
- Publication date Jul 14, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Jin Ping Liu
- H01 - BASIC ELECTRIC ELEMENTS

Jin Ping Liu

Person

Patents Grantslast 30 patents

Reliable non-volatile memory device

Strained channel transistor structure and method

Strained channel transistor structure and method

Method of forming a relaxed semiconductor buffer layer on a substra...

Silicon-germanium virtual substrate and method of fabricating the same

Method of forming a relaxed semiconductor buffer layer on a substra...

Patents Applicationslast 30 patents

RELIABLE NON-VOLATILE MEMORY DEVICE

STRAINED CHANNEL TRANSISTOR STRUCTURE AND METHOD

INTEGRATED CIRCUIT SYSTEM EMPLOYING STRESS-ENGINEERED LAYERS

STRAINED CHANNEL TRANSISTOR STRUCTURE AND METHOD

INTEGRATED CIRCUIT SYSTEM EMPLOYING DIFFUSED SOURCE/DRAIN EXTENSIONS

Method of forming a relaxed semiconductor buffer layer on a substra...

Method of forming a relaxed semiconductor buffer layer on a substra...

Silicon - germanium virtual substrate and method of fabricating the...