Jing Ling

Person

Milpitas, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Fast memory ECC error correction
- Patent number 12,242,342
- Issue date Mar 4, 2025
- Intel Corporation
- Jing Ling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive error correction to improve system memory reliability, ava...
- Patent number 12,235,720
- Issue date Feb 25, 2025
- Intel Corporation
- Rajat Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method to flush modified data from a volatil...
- Patent number 11,036,634
- Issue date Jun 15, 2021
- Intel Corporation
- Wei Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Boot process with parallel memory initialization
- Patent number 10,346,177
- Issue date Jul 9, 2019
- Intel Corporation
- Mahesh S. Natu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, system, and method to flush modified data from a volatil...
- Patent number 10,198,354
- Issue date Feb 5, 2019
- Intel Corporation
- Wei Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically changing lockstep configuration
- Patent number 9,697,094
- Issue date Jul 4, 2017
- Intel Corporation
- Debaleena Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Differential delay compensation
- Patent number 9,430,378
- Issue date Aug 30, 2016
- Micron Technology, Inc.
- Jing Ling
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Differential delay compensation
- Patent number 9,110,794
- Issue date Aug 18, 2015
- Micron Technology, Inc.
- Jing Ling
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Differential delay compensation
- Patent number 8,488,631
- Issue date Jul 16, 2013
- Micron Technology, Inc.
- Jing Ling
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Differential delay compensation
- Patent number 8,018,926
- Issue date Sep 13, 2011
- Jing Ling
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus enabling concurrent processing of contiguously...
- Patent number 7,656,891
- Issue date Feb 2, 2010
- Intel Corporation
- Juan-Carlos Calderon
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for detecting and managing loss of alignment i...
- Patent number 7,606,269
- Issue date Oct 20, 2009
- Intel Corporation
- Soowan Suh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Transporting stream client signals via packet interface using GFP m...
- Patent number 7,583,599
- Issue date Sep 1, 2009
- Intel Corporation
- Jing Ling
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for group alarm indication signal generation and clearing
- Patent number 7,564,777
- Issue date Jul 21, 2009
- Intel Corporation
- Soowan Suh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Control mechanism for mapping cells and packets
- Patent number 7,525,977
- Issue date Apr 28, 2009
- Intel Corporation
- Eduard Lecha
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus differential delay compensation processing of...
- Patent number 7,508,830
- Issue date Mar 24, 2009
- Intel Corporation
- Soowan Suh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Enhanced SDRAM bandwidth usage and memory management for TDM traffic
- Patent number 7,460,545
- Issue date Dec 2, 2008
- Intel Corporation
- Juan-Carlos Calderon
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and apparatus for centralized processing of contiguously and...
- Patent number 7,298,744
- Issue date Nov 20, 2007
- Intel Corporation
- Soowan Suh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Virtual output queue (VoQ) management method and apparatus
- Patent number 7,295,564
- Issue date Nov 13, 2007
- Intel Corporation
- Jing Ling
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Rate policing algorithm for packet flows
- Patent number 7,154,853
- Issue date Dec 26, 2006
- Intel Corporation
- Jean-Michel Caia
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Increasing memory access efficiency for packet applications
- Patent number 7,065,628
- Issue date Jun 20, 2006
- Intel Corporation
- Juan-Carlos Calderon
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Rate-based scheduling for packet applications
- Patent number 7,061,867
- Issue date Jun 13, 2006
- Intel Corporation
- Anguo T. Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Interleaving memory access
- Patent number 6,944,728
- Issue date Sep 13, 2005
- Intel Corporation
- Juan-Carlos Calderon
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamic memory allocation for assigning partitions to a logical por...
- Patent number 6,892,284
- Issue date May 10, 2005
- Intel Corporation
- Jing Ling
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHOD TO REDUCE MEMORY POWER CONSUMPTION IN A MEMORY...
- Publication number 20240193109
- Publication date Jun 13, 2024
- Intel Corporation
- Michelle M. WIGTON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE ERROR CORRECTION TO IMPROVE SYSTEM MEMORY RELIABILITY, AVA...
- Publication number 20240061741
- Publication date Feb 22, 2024
- Intel Corporation
- Rajat AGARWAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY TRANSACTION QUEUE BYPASS BASED ON CONFIGURABLE ADDRESS AND B...
- Publication number 20220179797
- Publication date Jun 9, 2022
- Intel Corporation
- Jeffrey C. Swanson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST MEMORY ECC ERROR CORRECTION
- Publication number 20220107866
- Publication date Apr 7, 2022
- Intel Corporation
- Jing LING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESS GENERATION FOR ADAPTIVE DOUBLE DEVICE DATA CORRECTION SPARING
- Publication number 20220108764
- Publication date Apr 7, 2022
- Intel Corporation
- Jing LING
- G11 - INFORMATION STORAGE
Information Patent Application
DETECTION OF DATA CORRUPTION IN MEMORY ADDRESS DECODE CIRCUITRY
- Publication number 20220091764
- Publication date Mar 24, 2022
- Intel Corporation
- Sreenivas MANDAVA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS, SYSTEM, AND METHOD TO FLUSH MODIFIED DATA FROM A VOLATIL...
- Publication number 20190171568
- Publication date Jun 6, 2019
- Intel Corporation
- Wei CHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS, SYSTEM, AND METHOD TO FLUSH MODIFIED DATA FROM A VOLATIL...
- Publication number 20180276124
- Publication date Sep 27, 2018
- Intel Corporation
- Wei CHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Boot Process with Parallel Memory Initialization
- Publication number 20180165100
- Publication date Jun 14, 2018
- Intel Corporation
- Mahesh S. Natu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY CHANGING LOCKSTEP CONFIGURATION
- Publication number 20160232063
- Publication date Aug 11, 2016
- Intel Corporation
- Debaleena Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIFFERENTIAL DELAY COMPENSATION
- Publication number 20150350114
- Publication date Dec 3, 2015
- Micron Technology, Inc.
- Jing Ling
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DIFFERENTIAL DELAY COMPENSATION
- Publication number 20130305010
- Publication date Nov 14, 2013
- Jing Ling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIFFERENTIAL DELAY COMPENSATION
- Publication number 20110317721
- Publication date Dec 29, 2011
- Jing Ling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Shared buffer for near-end and optical interface flow control in fi...
- Publication number 20070233894
- Publication date Oct 4, 2007
- Jing Ling
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Configurable bandwidth allocation for data channels accessing a mem...
- Publication number 20070089030
- Publication date Apr 19, 2007
- Alejandro Lenero Lenero Beracoechea
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Techniques to buffer traffic in a communications system
- Publication number 20070086479
- Publication date Apr 19, 2007
- Jing Ling
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Techniques for group alarm indication signal generation and clearing
- Publication number 20060256710
- Publication date Nov 16, 2006
- Intel Corporation
- Soowan Suh
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Differential delay compensation
- Publication number 20060221944
- Publication date Oct 5, 2006
- Intel Corporation
- Jing Ling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Virtual output queue (VoQ) management method and apparatus
- Publication number 20040131069
- Publication date Jul 8, 2004
- Jing Ling
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Memory management free pointer pool
- Publication number 20040131055
- Publication date Jul 8, 2004
- Juan-Carlos Calderon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interleaving memory access
- Publication number 20040123056
- Publication date Jun 24, 2004
- Intel Corporation
- Juan-Carlos Calderon
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Dynamic memory allocation for packet interfaces
- Publication number 20040049650
- Publication date Mar 11, 2004
- Jing Ling
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Buffer memory reservation
- Publication number 20030223442
- Publication date Dec 4, 2003
- Anguo T. Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Increasing memory access efficiency for packet applications
- Publication number 20030225991
- Publication date Dec 4, 2003
- Juan-Carlos Calderon
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Rate policing algorithm for packet flows
- Publication number 20030206522
- Publication date Nov 6, 2003
- Jean-Michel Caia
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Rate-based scheduling for packet applications
- Publication number 20030185155
- Publication date Oct 2, 2003
- Anguo T. Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Person

Patents Grantslast 30 patents

Fast memory ECC error correction

Adaptive error correction to improve system memory reliability, ava...

Apparatus, system, and method to flush modified data from a volatil...

Boot process with parallel memory initialization

Apparatus, system, and method to flush modified data from a volatil...

Dynamically changing lockstep configuration

Differential delay compensation

Differential delay compensation

Differential delay compensation

Differential delay compensation

Method and apparatus enabling concurrent processing of contiguously...

Method and apparatus for detecting and managing loss of alignment i...

Transporting stream client signals via packet interface using GFP m...

Techniques for group alarm indication signal generation and clearing

Control mechanism for mapping cells and packets

Method and apparatus differential delay compensation processing of...

Enhanced SDRAM bandwidth usage and memory management for TDM traffic

Method and apparatus for centralized processing of contiguously and...

Virtual output queue (VoQ) management method and apparatus

Rate policing algorithm for packet flows

Increasing memory access efficiency for packet applications

Rate-based scheduling for packet applications

Interleaving memory access

Dynamic memory allocation for assigning partitions to a logical por...

Patents Applicationslast 30 patents

APPARATUS AND METHOD TO REDUCE MEMORY POWER CONSUMPTION IN A MEMORY...

ADAPTIVE ERROR CORRECTION TO IMPROVE SYSTEM MEMORY RELIABILITY, AVA...

MEMORY TRANSACTION QUEUE BYPASS BASED ON CONFIGURABLE ADDRESS AND B...

FAST MEMORY ECC ERROR CORRECTION

ADDRESS GENERATION FOR ADAPTIVE DOUBLE DEVICE DATA CORRECTION SPARING

DETECTION OF DATA CORRUPTION IN MEMORY ADDRESS DECODE CIRCUITRY

APPARATUS, SYSTEM, AND METHOD TO FLUSH MODIFIED DATA FROM A VOLATIL...

APPARATUS, SYSTEM, AND METHOD TO FLUSH MODIFIED DATA FROM A VOLATIL...

Boot Process with Parallel Memory Initialization

DYNAMICALLY CHANGING LOCKSTEP CONFIGURATION

DIFFERENTIAL DELAY COMPENSATION

DIFFERENTIAL DELAY COMPENSATION

DIFFERENTIAL DELAY COMPENSATION

Shared buffer for near-end and optical interface flow control in fi...

Configurable bandwidth allocation for data channels accessing a mem...

Techniques to buffer traffic in a communications system

Techniques for group alarm indication signal generation and clearing

Differential delay compensation

Virtual output queue (VoQ) management method and apparatus

Memory management free pointer pool

Interleaving memory access

Dynamic memory allocation for packet interfaces

Buffer memory reservation

Increasing memory access efficiency for packet applications

Rate policing algorithm for packet flows

Rate-based scheduling for packet applications