Jinyong Yuan

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Structures for LUT-based arithmetic in PLDs
- Patent number 9,658,830
- Issue date May 23, 2017
- Altera Corporation
- Ketan Padalia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device having logic elements with dedicated hard...
- Patent number 9,172,378
- Issue date Oct 27, 2015
- Altera Corporation
- Michael D. Hutton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Register retiming technique
- Patent number 9,053,274
- Issue date Jun 9, 2015
- Altera Corporation
- Babette van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register retiming technique
- Patent number 8,806,399
- Issue date Aug 12, 2014
- Altera Corporation
- Babette van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device having logic elements with dedicated hard...
- Patent number 8,601,424
- Issue date Dec 3, 2013
- Altera Corporation
- Michael D. Hutton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reassembling scattered logic blocks in integrated circuits
- Patent number 8,443,327
- Issue date May 14, 2013
- Altera Corporation
- Mohd Mawardi Bin Mohd Razha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphical user aid for technology migration and associated methods
- Patent number 8,397,185
- Issue date Mar 12, 2013
- Altera Corporation
- Steven Perry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible RAM clock enable
- Patent number 8,271,821
- Issue date Sep 18, 2012
- Altera Corporation
- Jinyong Yuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Partial compilation of circuit design with new software version to...
- Patent number 8,245,163
- Issue date Aug 14, 2012
- Altera Corporation
- Jinyong Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphical user aid for technology migration and associated methods
- Patent number 8,191,020
- Issue date May 29, 2012
- Altera Corporation
- Steven Perry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Gated clock conversion
- Patent number 8,006,206
- Issue date Aug 23, 2011
- Altera Corporation
- Jinyong Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of verifying functional equivalence between FPGA and struct...
- Patent number 7,992,110
- Issue date Aug 2, 2011
- Altera Corporation
- Jinyong Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device having logic elements with dedicated hard...
- Patent number 7,890,910
- Issue date Feb 15, 2011
- Altera Corporation
- Michael D. Hutton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
SAT-based technology mapping framework
- Patent number 7,725,871
- Issue date May 25, 2010
- Altera Corporation
- Sean A. Safarpour
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device having logic elements with dedicated hard...
- Patent number 7,705,628
- Issue date Apr 27, 2010
- Altera Corporation
- Michael D. Hutton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Graphical user aid for technology migration and associated methods
- Patent number 7,631,284
- Issue date Dec 8, 2009
- Altera Corporation
- Steven Perry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
User-directed timing-driven synthesis
- Patent number 7,587,688
- Issue date Sep 8, 2009
- Altera Corporation
- Babette Van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structures for LUT-based arithmetic in PLDs
- Patent number 7,558,812
- Issue date Jul 7, 2009
- Altera Corporation
- Ketan Padalia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Gated clock conversion
- Patent number 7,424,689
- Issue date Sep 9, 2008
- Altera Corporation
- Jinyong Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing synthesis runtime
- Patent number 7,415,693
- Issue date Aug 19, 2008
- Altera Corporation
- Babette van Antwerpen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for producing mappings of logic suitable for FPGA and struc...
- Patent number 7,406,668
- Issue date Jul 29, 2008
- Altera Corporation
- Bruce Pedersen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible RAM clock enable
- Patent number 7,397,726
- Issue date Jul 8, 2008
- Altera Corporation
- Jinyong Yuan
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods of verifying functional equivalence between FPGA and struct...
- Patent number 7,386,819
- Issue date Jun 10, 2008
- Altera Corporation
- Jinyong Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SAT-based technology mapping framework
- Patent number 7,386,828
- Issue date Jun 10, 2008
- Altera Corporation
- Sean A. Safarpour
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for improved structured ASIC design
- Patent number 7,373,630
- Issue date May 13, 2008
- Altera Corporation
- Jinyong Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of producing application-specific integrated circuit equiva...
- Patent number 7,373,631
- Issue date May 13, 2008
- Altera Corporation
- Jinyong Yuan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for storing and naming static library cells for lookup by l...
- Patent number 7,363,596
- Issue date Apr 22, 2008
- Altera Corporation
- Ji Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for producing equivalent logic designs for FPGAs and struct...
- Patent number 7,360,197
- Issue date Apr 15, 2008
- Altera Corporation
- James G Schleicher, II
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area efficient fractureable logic elements
- Patent number 7,330,052
- Issue date Feb 12, 2008
- Altera Corporation
- Sinan Kaptanoglu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for performing mapping onto field programmable...
- Patent number 7,308,671
- Issue date Dec 11, 2007
- Altera Corporation
- Jinyong Yuan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
STRUCTURES FOR LUT-BASED ARITHMETIC IN PLDS
- Publication number 20170322775
- Publication date Nov 9, 2017
- Altera Corporation
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REASSEMBLING SCATTERED LOGIC BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20120216165
- Publication date Aug 23, 2012
- Mohd Mowardi Bin Mohd Razha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flexible RAM Clock Enable
- Publication number 20080253220
- Publication date Oct 16, 2008
- Altera Corporation
- Jinyong Yuan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Area efficient fractureable logic elements
- Publication number 20070063732
- Publication date Mar 22, 2007
- Altera Corporation
- Sinan Kaptanoglu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Methods for creating and expanding libraries of structured ASIC log...
- Publication number 20060230376
- Publication date Oct 12, 2006
- Altera Corporation
- Jinyong Yuan
- G06 - COMPUTING CALCULATING COUNTING

Jinyong Yuan

Person

Patents Grantslast 30 patents

Structures for LUT-based arithmetic in PLDs

Programmable logic device having logic elements with dedicated hard...

Register retiming technique

Register retiming technique

Programmable logic device having logic elements with dedicated hard...

Reassembling scattered logic blocks in integrated circuits

Graphical user aid for technology migration and associated methods

Flexible RAM clock enable

Partial compilation of circuit design with new software version to...

Graphical user aid for technology migration and associated methods

Gated clock conversion

Methods of verifying functional equivalence between FPGA and struct...

Programmable logic device having logic elements with dedicated hard...

SAT-based technology mapping framework

Programmable logic device having logic elements with dedicated hard...

Graphical user aid for technology migration and associated methods

User-directed timing-driven synthesis

Structures for LUT-based arithmetic in PLDs

Gated clock conversion

Method and apparatus for reducing synthesis runtime

Methods for producing mappings of logic suitable for FPGA and struc...

Flexible RAM clock enable

Methods of verifying functional equivalence between FPGA and struct...

SAT-based technology mapping framework

Methods for improved structured ASIC design

Methods of producing application-specific integrated circuit equiva...

Methods for storing and naming static library cells for lookup by l...

Methods for producing equivalent logic designs for FPGAs and struct...

Area efficient fractureable logic elements

Method and apparatus for performing mapping onto field programmable...

Patents Applicationslast 30 patents

STRUCTURES FOR LUT-BASED ARITHMETIC IN PLDS

REASSEMBLING SCATTERED LOGIC BLOCKS IN INTEGRATED CIRCUITS

Flexible RAM Clock Enable

Area efficient fractureable logic elements

Methods for creating and expanding libraries of structured ASIC log...