Jiong-Ping Lu

Person

Dallas, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low stress sacrificial cap layer
- Patent number 9,048,180
- Issue date Jun 2, 2015
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nickel silicide formation for semiconductor components
- Patent number 8,546,259
- Issue date Oct 1, 2013
- Texas Instruments Incorporated
- Juanita DeLoach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming capacitors
- Patent number 8,088,659
- Issue date Jan 3, 2012
- Micron Technology, Inc.
- Jiong-Ping Lu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Capacitor formed on a recrystallized polysilicon layer
- Patent number 8,053,296
- Issue date Nov 8, 2011
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low stress sacrificial cap layer
- Patent number 7,994,073
- Issue date Aug 9, 2011
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FUSI integration method using SOG as a sacrificial planarization layer
- Patent number 7,943,499
- Issue date May 17, 2011
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-K dielectric materials and processes for manufacturing them
- Patent number 7,732,852
- Issue date Jun 8, 2010
- Micron Technology, Inc.
- Jiong-Ping Lu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
FUSI integration method using SOG as a sacrificial planarization layer
- Patent number 7,732,312
- Issue date Jun 8, 2010
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FUSI integration method using SOG as a sacrificial planarization layer
- Patent number 7,732,313
- Issue date Jun 8, 2010
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for improving the thermal stability of silicide
- Patent number 7,666,729
- Issue date Feb 23, 2010
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
In-situ co-deposition of Si in diffusion barrier material depositio...
- Patent number 7,655,555
- Issue date Feb 2, 2010
- Texas Instruments Incorporated
- Richard A. Faust
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a fully silicided semiconductor device with indep...
- Patent number 7,585,738
- Issue date Sep 8, 2009
- Texas Instruments Incorporated
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-k dielectric materials and processes for manufacturing them
- Patent number 7,544,987
- Issue date Jun 9, 2009
- Micron Technology, Inc.
- Jiong-Ping Lu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Process method to facilitate silicidation
- Patent number 7,448,395
- Issue date Nov 11, 2008
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a semiconductor device having silicided re...
- Patent number 7,422,968
- Issue date Sep 9, 2008
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a semiconductor device containing metal si...
- Patent number 7,422,967
- Issue date Sep 9, 2008
- Texas Instruments Incorporated
- Juanita DeLoach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a silicided gate electrode and method o...
- Patent number 7,348,265
- Issue date Mar 25, 2008
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a silicided gate electrode using a buffer...
- Patent number 7,341,933
- Issue date Mar 11, 2008
- Texas Instruments Incorporated
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a semiconductor device having a silicided...
- Patent number 7,338,888
- Issue date Mar 4, 2008
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicide formation using a low temperature anneal process
- Patent number 7,335,595
- Issue date Feb 26, 2008
- Texas Instruments Incorporated
- Lance S. Robertson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating dual work function metal gates
- Patent number 7,253,049
- Issue date Aug 7, 2007
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for defect reduction in electrochemical plating
- Patent number 7,253,124
- Issue date Aug 7, 2007
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit metal silicide method
- Patent number 7,208,409
- Issue date Apr 24, 2007
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plating-rinse-plating process for fabricating copper interconnects
- Patent number 7,198,705
- Issue date Apr 3, 2007
- Texas Instruments Incorporated
- Linlin Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal silicide induced lateral excessive encroachment reduction by...
- Patent number 7,199,032
- Issue date Apr 3, 2007
- Texas Instruments Incorporated
- Duofeng Yue
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration scheme for using silicided dual work function metal gates
- Patent number 7,183,187
- Issue date Feb 27, 2007
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having a fully silicided gate electrode and me...
- Patent number 7,148,143
- Issue date Dec 12, 2006
- Texas Instruments Incorporated
- Haowen Bu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor devices and methods of manufacturing such semiconduct...
- Patent number 7,101,788
- Issue date Sep 5, 2006
- Texas Instruments Incorporated
- Patricia Beauregard Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
NiSi metal gate stacks using a boron-trap
- Patent number 7,098,094
- Issue date Aug 29, 2006
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicide method for CMOS integrated circuits
- Patent number 7,029,967
- Issue date Apr 18, 2006
- Texas Instruments Incorporated
- Song Zhao
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Method for Improving the Thermal Stability of Silicide
- Publication number 20110151637
- Publication date Jun 23, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR IMPROVING THE THERMAL STABILITY OF SILICIDE
- Publication number 20100317170
- Publication date Dec 16, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NOVEL HIGH-K DIELECTRIC MATERIALS AND PROCESSES FOR MANUFACTURING THEM
- Publication number 20100227450
- Publication date Sep 9, 2010
- Micron Technology, Inc.
- Jiong-Ping Lu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
CAPACITOR FORMED ON A RECRYSTALLIZED POLYSILICON LAYER
- Publication number 20100159665
- Publication date Jun 24, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FUSI Integration Method Using SOG as a Sacrificial Planarization Layer
- Publication number 20100041231
- Publication date Feb 18, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FUSI INTEGRATION METHOD USING SOG AS A SACRIFICIAL PLANARIZATION LAYER
- Publication number 20090111224
- Publication date Apr 30, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NICKEL SILICIDE FORMATION FOR SEMICONDUCTOR COMPONENTS
- Publication number 20090079010
- Publication date Mar 26, 2009
- Juanita DeLoach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING A FULLY SILICIDED SEMICONDUCTOR DEVICE WITH INDEP...
- Publication number 20080265420
- Publication date Oct 30, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of Forming a Fully Silicided Semiconductor Device with Indep...
- Publication number 20080265345
- Publication date Oct 30, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process method to optimize fully silicided gate (FUSI) thru PAI imp...
- Publication number 20080206973
- Publication date Aug 28, 2008
- Texas Instrument Inc.
- Frank Scott Johnson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ebeam inspection for detecting gate dielectric punch through and/or...
- Publication number 20080176345
- Publication date Jul 24, 2008
- Texas Instruments Inc.
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE HAVING A SILICIDED GATE ELECTRODE AND METHOD O...
- Publication number 20080135945
- Publication date Jun 12, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low Stress Sacrificial Cap Layer
- Publication number 20080064175
- Publication date Mar 13, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low Stress Sacrificial Cap Layer
- Publication number 20070269951
- Publication date Nov 22, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FUSI integration method using SOG as a sacrificial planarization layer
- Publication number 20070173047
- Publication date Jul 26, 2007
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process For Selectively Removing Dielectric Material in the Presenc...
- Publication number 20070161246
- Publication date Jul 12, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Yaw S. Obeng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating a transistor using a low temperature spike a...
- Publication number 20070099407
- Publication date May 3, 2007
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Novel high-k dielectric materials and processes for manufacturing them
- Publication number 20060270148
- Publication date Nov 30, 2006
- Jiong-Ping Lu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Novel method for manufacturing a semiconductor device containing me...
- Publication number 20060258091
- Publication date Nov 16, 2006
- Texas Instruments Inc.
- Juanita DeLoach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Improving the Thermal Stability of Silicide
- Publication number 20060246668
- Publication date Nov 2, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for fabricating dual work function metal gates
- Publication number 20060134844
- Publication date Jun 22, 2006
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for manufacturing a silicided gate electrode using a buffer...
- Publication number 20060121713
- Publication date Jun 8, 2006
- Texas Instruments, Inc.
- Shaofeng Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for improving the thermal stability of silicide
- Publication number 20060040438
- Publication date Feb 23, 2006
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for manufacturing a semiconductor device having silicided re...
- Publication number 20060024882
- Publication date Feb 2, 2006
- Texas Instruments, Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for reducing metal silicide excessive encroachment defects i...
- Publication number 20060024938
- Publication date Feb 2, 2006
- Texas Instruments, Incorporated
- Duofeng Yue
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Metal silicide induced lateral excessive encroachment reduction by...
- Publication number 20060024935
- Publication date Feb 2, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Duofeng Yue
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicide method for CMOS integrated circuits
- Publication number 20060019478
- Publication date Jan 26, 2006
- Song Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicide formation using a low temperature anneal process
- Publication number 20060014387
- Publication date Jan 19, 2006
- Lance S. Robertson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process method to facilitate silicidation
- Publication number 20060014393
- Publication date Jan 19, 2006
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integration scheme for using silicided dual work function metal gates
- Publication number 20050260841
- Publication date Nov 24, 2005
- Texas Instruments, Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS

Jiong-Ping Lu

Person

Patents Grantslast 30 patents

Low stress sacrificial cap layer

Nickel silicide formation for semiconductor components

Method of forming capacitors

Capacitor formed on a recrystallized polysilicon layer

Low stress sacrificial cap layer

FUSI integration method using SOG as a sacrificial planarization layer

High-K dielectric materials and processes for manufacturing them

FUSI integration method using SOG as a sacrificial planarization layer

FUSI integration method using SOG as a sacrificial planarization layer

Method for improving the thermal stability of silicide

In-situ co-deposition of Si in diffusion barrier material depositio...

Method of forming a fully silicided semiconductor device with indep...

High-k dielectric materials and processes for manufacturing them

Process method to facilitate silicidation

Method for manufacturing a semiconductor device having silicided re...

Method for manufacturing a semiconductor device containing metal si...

Semiconductor device having a silicided gate electrode and method o...

Method for manufacturing a silicided gate electrode using a buffer...

Method for manufacturing a semiconductor device having a silicided...

Silicide formation using a low temperature anneal process

Method for fabricating dual work function metal gates

Process for defect reduction in electrochemical plating

Integrated circuit metal silicide method

Plating-rinse-plating process for fabricating copper interconnects

Metal silicide induced lateral excessive encroachment reduction by...

Integration scheme for using silicided dual work function metal gates

Semiconductor device having a fully silicided gate electrode and me...

Semiconductor devices and methods of manufacturing such semiconduct...

NiSi metal gate stacks using a boron-trap

Silicide method for CMOS integrated circuits

Patents Applicationslast 30 patents

Method for Improving the Thermal Stability of Silicide

METHOD FOR IMPROVING THE THERMAL STABILITY OF SILICIDE

NOVEL HIGH-K DIELECTRIC MATERIALS AND PROCESSES FOR MANUFACTURING THEM

CAPACITOR FORMED ON A RECRYSTALLIZED POLYSILICON LAYER

FUSI Integration Method Using SOG as a Sacrificial Planarization Layer

FUSI INTEGRATION METHOD USING SOG AS A SACRIFICIAL PLANARIZATION LAYER

NICKEL SILICIDE FORMATION FOR SEMICONDUCTOR COMPONENTS

METHOD OF FORMING A FULLY SILICIDED SEMICONDUCTOR DEVICE WITH INDEP...

Method of Forming a Fully Silicided Semiconductor Device with Indep...

Process method to optimize fully silicided gate (FUSI) thru PAI imp...

Ebeam inspection for detecting gate dielectric punch through and/or...

SEMICONDUCTOR DEVICE HAVING A SILICIDED GATE ELECTRODE AND METHOD O...

Low Stress Sacrificial Cap Layer

Low Stress Sacrificial Cap Layer

FUSI integration method using SOG as a sacrificial planarization layer

Process For Selectively Removing Dielectric Material in the Presenc...

Method for fabricating a transistor using a low temperature spike a...

Novel high-k dielectric materials and processes for manufacturing them

Novel method for manufacturing a semiconductor device containing me...

Method for Improving the Thermal Stability of Silicide

Method for fabricating dual work function metal gates

Method for manufacturing a silicided gate electrode using a buffer...

Method for improving the thermal stability of silicide

Method for manufacturing a semiconductor device having silicided re...

Method for reducing metal silicide excessive encroachment defects i...

Metal silicide induced lateral excessive encroachment reduction by...

Silicide method for CMOS integrated circuits

Silicide formation using a low temperature anneal process

Process method to facilitate silicidation

Integration scheme for using silicided dual work function metal gates