Jiung Wu

Person

Kueishan Shiang, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Profile of through via protrusion in 3DIC interconnect
- Patent number 11,004,741
- Issue date May 11, 2021
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jiung Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Profile of through via protrusion in 3DIC interconnect
- Patent number 10,566,237
- Issue date Feb 18, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jiung Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Profile of through via protrusion in 3DIC interconnect
- Patent number 10,163,705
- Issue date Dec 25, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jiung Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-alignment for redistribution layer
- Patent number 10,074,595
- Issue date Sep 11, 2018
- Taiwan Semiconductor Manufacturing Company
- Ku-Feng Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-alignment for redistribution layer
- Patent number 9,786,580
- Issue date Oct 10, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ku-Feng Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reducing substrate warpage in semiconductor processing
- Patent number 8,691,706
- Issue date Apr 8, 2014
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...

Patents Applicationslast 30 patents

Information Patent Application
PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
- Publication number 20250038073
- Publication date Jan 30, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ke-Han SHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE STACKING STRUCTURE, SEMICONDUCTOR PACKAGE AND FORMATION METHOD...
- Publication number 20230369156
- Publication date Nov 16, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Su-Chun Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE STACKING STRUCTURE, SEMICONDUCTOR PACKAGE AND MANUFACTURING MET...
- Publication number 20230360993
- Publication date Nov 9, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Su-Chun Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Profile of Through Via Protrusion in 3DIC Interconnect
- Publication number 20200144119
- Publication date May 7, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jiung Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Profile of Through Via Protrusion in 3DIC Interconnect
- Publication number 20190122927
- Publication date Apr 25, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jiung Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-Alignment for Redistribution Layer
- Publication number 20180012825
- Publication date Jan 11, 2018
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ku-Feng Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Profile of Through Via Protrusion in 3DIC Interconnect
- Publication number 20150311141
- Publication date Oct 29, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jiung Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNMENT FOR REDISTRIBUTION LAYER
- Publication number 20150137382
- Publication date May 21, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ku-Feng Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Reducing Substrate Warpage in Semiconductor Processing
- Publication number 20130183831
- Publication date Jul 18, 2013
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chen-Hua Yu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...

Person

Patents Grantslast 30 patents

Profile of through via protrusion in 3DIC interconnect

Profile of through via protrusion in 3DIC interconnect

Profile of through via protrusion in 3DIC interconnect

Self-alignment for redistribution layer

Self-alignment for redistribution layer

Reducing substrate warpage in semiconductor processing

Patents Applicationslast 30 patents

PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME

DIE STACKING STRUCTURE, SEMICONDUCTOR PACKAGE AND FORMATION METHOD...

DIE STACKING STRUCTURE, SEMICONDUCTOR PACKAGE AND MANUFACTURING MET...

Profile of Through Via Protrusion in 3DIC Interconnect

Profile of Through Via Protrusion in 3DIC Interconnect

Self-Alignment for Redistribution Layer

Profile of Through Via Protrusion in 3DIC Interconnect

SELF-ALIGNMENT FOR REDISTRIBUTION LAYER

Reducing Substrate Warpage in Semiconductor Processing