Joachim Keinert

Person

Altdorf, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit design changes using through-silicon vias
- Patent number 10,956,644
- Issue date Mar 23, 2021
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layouting of interconnect lines in integrated circuits
- Patent number 10,579,773
- Issue date Mar 3, 2020
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,534,884
- Issue date Jan 14, 2020
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,417,366
- Issue date Sep 17, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layouting of interconnect lines in integrated circuits
- Patent number 10,417,377
- Issue date Sep 17, 2019
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,366,191
- Issue date Jul 30, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,242,140
- Issue date Mar 26, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 10,235,487
- Issue date Mar 19, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement clustering-based white space reservation
- Patent number 10,223,489
- Issue date Mar 5, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design changes using through-silicon vias
- Patent number 10,223,491
- Issue date Mar 5, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area sharing between multiple large block synthesis (LBS) blocks
- Patent number 10,169,519
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layouting of interconnect lines in integrated circuits
- Patent number 10,013,521
- Issue date Jul 3, 2018
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area sharing between multiple large block synthesis (LBS) blocks
- Patent number 9,946,830
- Issue date Apr 17, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout of large block synthesis blocks in integrated circuits
- Patent number 9,928,329
- Issue date Mar 27, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enabling an incremental sign-off process using design data
- Patent number 9,922,154
- Issue date Mar 20, 2018
- International Business Machines Corporation
- Hans-Werner Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write-bitline control in multicore SRAM arrays
- Patent number 9,761,304
- Issue date Sep 12, 2017
- International Business Machines Corporation
- Joachim Keinert
- G11 - INFORMATION STORAGE
Information Patent Grant
De-coupling capacitance placement
- Patent number 9,684,759
- Issue date Jun 20, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
De-coupling capacitance placement
- Patent number 9,679,099
- Issue date Jun 13, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Through-silicon via access device for integrated circuits
- Patent number 9,633,928
- Issue date Apr 25, 2017
- International Business Machines Corporation
- Harry Barowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit design changes using through-silicon vias
- Patent number 9,569,580
- Issue date Feb 14, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit design changes using through-silicon vias
- Patent number 9,501,603
- Issue date Nov 22, 2016
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Through-silicon via access device for integrated circuits
- Patent number 9,412,682
- Issue date Aug 9, 2016
- International Business Machines Corporation
- Harry Barowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Charge recycling between power domains of integrated circuits
- Patent number 8,984,314
- Issue date Mar 17, 2015
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Charge recycling between power domains of integrated circuits
- Patent number 8,972,758
- Issue date Mar 3, 2015
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit macro placement using macro aspect ratio based on ports
- Patent number 8,762,919
- Issue date Jun 24, 2014
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shaping ports in integrated circuit design
- Patent number 8,495,551
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing secondary power pins in integrated circuit design
- Patent number 8,495,547
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performing reliability analysis of signal wires
- Patent number 8,463,571
- Issue date Jun 11, 2013
- International Business Machines Corporation
- Soroush Abbaspour
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Post timing layout modification for performance
- Patent number 8,448,124
- Issue date May 21, 2013
- International Business Machines Corporation
- Uwe Fassnacht
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, electronic design automation tool, computer program product...
- Patent number 8,429,584
- Issue date Apr 23, 2013
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20190294739
- Publication date Sep 26, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS
- Publication number 20190220570
- Publication date Jul 18, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20190065635
- Publication date Feb 28, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20190065636
- Publication date Feb 28, 2019
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS
- Publication number 20180285514
- Publication date Oct 4, 2018
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS
- Publication number 20180285513
- Publication date Oct 4, 2018
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AREA SHARING BETWEEN MULTIPLE LARGE BLOCK SYNTHESIS (LBS) BLOCKS
- Publication number 20180189439
- Publication date Jul 5, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLACEMENT CLUSTERING-BASED WHITE SPACE RESERVATION
- Publication number 20180150584
- Publication date May 31, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20180101625
- Publication date Apr 12, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20180101626
- Publication date Apr 12, 2018
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AREA SHARING BETWEEN MULTIPLE LARGE BLOCK SYNTHESIS (LBS) BLOCKS
- Publication number 20170351798
- Publication date Dec 7, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENABLING AN INCREMENTAL SIGN-OFF PROCESS USING DESIGN DATA
- Publication number 20170337314
- Publication date Nov 23, 2017
- International Business Machines Corporation
- Hans-Werner Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20170212969
- Publication date Jul 27, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS
- Publication number 20170212970
- Publication date Jul 27, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS
- Publication number 20170154148
- Publication date Jun 1, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS
- Publication number 20170140088
- Publication date May 18, 2017
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DE-COUPLING CAPACITANCE PLACEMENT
- Publication number 20170004248
- Publication date Jan 5, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DE-COUPLING CAPACITANCE PLACEMENT
- Publication number 20170004239
- Publication date Jan 5, 2017
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS
- Publication number 20160070842
- Publication date Mar 10, 2016
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THROUGH-SILICON VIA ACCESS DEVICE FOR INTEGRATED CIRCUITS
- Publication number 20160071786
- Publication date Mar 10, 2016
- International Business Machines Corporation
- Harry Barowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS
- Publication number 20160070840
- Publication date Mar 10, 2016
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THROUGH-SILICON VIA ACCESS DEVICE FOR INTEGRATED CIRCUITS
- Publication number 20160071783
- Publication date Mar 10, 2016
- International Business Machines Corporation
- Harry Barowski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Charge Recycling Between Power Domains of Integrated Circuits
- Publication number 20140082386
- Publication date Mar 20, 2014
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Charge Recycling Between Power Domains of Integrated Circuits
- Publication number 20130138978
- Publication date May 30, 2013
- International Business Machines Corporation
- Harry Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POST TIMING LAYOUT MODIFICATION FOR PERFORMANCE
- Publication number 20130074025
- Publication date Mar 21, 2013
- International Business Machines Corporation
- Uwe Fassnacht
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING RELIABILITY ANALYSIS OF SIGNAL WIRES
- Publication number 20120123725
- Publication date May 17, 2012
- International Business Machines Corporation
- Soroush Abbaspour
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Using Port Obscurity Factors to Improve Routing
- Publication number 20120060139
- Publication date Mar 8, 2012
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit Macro Placement Using Macro Aspect Ratio Based on Ports
- Publication number 20110289468
- Publication date Nov 24, 2011
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Shaping Ports in Integrated Circuit Design
- Publication number 20110154283
- Publication date Jun 23, 2011
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and System for Providing Secondary Power Pins in Integrated...
- Publication number 20110113398
- Publication date May 12, 2011
- International Business Machines Corporation
- Joachim Keinert
- G06 - COMPUTING CALCULATING COUNTING

Joachim Keinert

Person

Patents Grantslast 30 patents

Integrated circuit design changes using through-silicon vias

Layouting of interconnect lines in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Layouting of interconnect lines in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Layout of large block synthesis blocks in integrated circuits

Placement clustering-based white space reservation

Integrated circuit design changes using through-silicon vias

Area sharing between multiple large block synthesis (LBS) blocks

Layouting of interconnect lines in integrated circuits

Area sharing between multiple large block synthesis (LBS) blocks

Layout of large block synthesis blocks in integrated circuits

Enabling an incremental sign-off process using design data

Write-bitline control in multicore SRAM arrays

De-coupling capacitance placement

De-coupling capacitance placement

Through-silicon via access device for integrated circuits

Integrated circuit design changes using through-silicon vias

Integrated circuit design changes using through-silicon vias

Through-silicon via access device for integrated circuits

Charge recycling between power domains of integrated circuits

Charge recycling between power domains of integrated circuits

Circuit macro placement using macro aspect ratio based on ports

Shaping ports in integrated circuit design

Providing secondary power pins in integrated circuit design

Performing reliability analysis of signal wires

Post timing layout modification for performance

Method, electronic design automation tool, computer program product...

Patents Applicationslast 30 patents

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS

LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS

AREA SHARING BETWEEN MULTIPLE LARGE BLOCK SYNTHESIS (LBS) BLOCKS

PLACEMENT CLUSTERING-BASED WHITE SPACE RESERVATION

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

AREA SHARING BETWEEN MULTIPLE LARGE BLOCK SYNTHESIS (LBS) BLOCKS

ENABLING AN INCREMENTAL SIGN-OFF PROCESS USING DESIGN DATA

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

LAYOUT OF LARGE BLOCK SYNTHESIS BLOCKS IN INTEGRATED CIRCUITS

INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS

LAYOUTING OF INTERCONNECT LINES IN INTEGRATED CIRCUITS

DE-COUPLING CAPACITANCE PLACEMENT

DE-COUPLING CAPACITANCE PLACEMENT

INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS

THROUGH-SILICON VIA ACCESS DEVICE FOR INTEGRATED CIRCUITS

INTEGRATED CIRCUIT DESIGN CHANGES USING THROUGH-SILICON VIAS

THROUGH-SILICON VIA ACCESS DEVICE FOR INTEGRATED CIRCUITS

Charge Recycling Between Power Domains of Integrated Circuits

Charge Recycling Between Power Domains of Integrated Circuits

POST TIMING LAYOUT MODIFICATION FOR PERFORMANCE

PERFORMING RELIABILITY ANALYSIS OF SIGNAL WIRES

Using Port Obscurity Factors to Improve Routing

Circuit Macro Placement Using Macro Aspect Ratio Based on Ports

Shaping Ports in Integrated Circuit Design

Method and System for Providing Secondary Power Pins in Integrated...