Jochen Preiss

Person

Boeblingen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Binary logic unit and method to operate a binary logic unit
- Patent number 8,756,263
- Issue date Jun 17, 2014
- International Business Machines Corporation
- Tobias Gemmeke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reuse of rounder for fixed conversion of log instructions
- Patent number 8,626,807
- Issue date Jan 7, 2014
- International Business Machines Corporation
- Maarten Boersma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Zero indication forwarding for floating point unit power reduction
- Patent number 8,578,196
- Issue date Nov 5, 2013
- International Business Machines Corporation
- Harry S. Barowski
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Distributed residue-checking of a floating point unit
- Patent number 8,566,383
- Issue date Oct 22, 2013
- International Business Machines Corporation
- Son Trong Dao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary logic unit and method to operate a binary logic unit
- Patent number 8,452,824
- Issue date May 28, 2013
- International Business Machines Corporation
- Tobias Gemmeke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fast floating point compare with slower backup for corner cases
- Patent number 8,407,275
- Issue date Mar 26, 2013
- International Business Machines Corporation
- Maarten J. Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic computing circuit for operand width reduction for a modu...
- Patent number 8,370,409
- Issue date Feb 5, 2013
- International Business Machines Corporation
- Tobias Gemmeke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient forcing of corner cases in a floating point rounder
- Patent number 8,352,531
- Issue date Jan 8, 2013
- International Business Machines Corporation
- Maarten J. Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for storing numbers in first and second formats i...
- Patent number 8,346,828
- Issue date Jan 1, 2013
- International Business Machines Corporation
- Maarten Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shifter with all-one and all-zero detection using a portion of part...
- Patent number 8,332,453
- Issue date Dec 11, 2012
- International Business Machines Corporation
- Maarten Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supporting multiple formats in a floating point processor
- Patent number 8,291,003
- Issue date Oct 16, 2012
- International Business Machines Corporation
- Maarten J. Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Zero indication forwarding for floating point unit power reduction
- Patent number 8,255,726
- Issue date Aug 28, 2012
- International Business Machines Corporation
- Harry S. Barowski
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Normalizer shift prediction for log estimate instructions
- Patent number 8,244,783
- Issue date Aug 14, 2012
- International Business Machines Corporation
- Maarten J. Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3-stack floorplan for floating point unit
- Patent number 8,032,854
- Issue date Oct 4, 2011
- International Business Machines Corporation
- Maarten Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor chip with a plurality of scannable storage elements a...
- Patent number 7,996,738
- Issue date Aug 9, 2011
- International Business Machines Corporation
- Tobias Gemmeke
- G01 - MEASURING TESTING
Information Patent Grant
Design structure to reduce power consumption within a clock gated s...
- Patent number 7,735,038
- Issue date Jun 8, 2010
- International Business Machines Corporation
- Tobias Gemmeke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multiplexing output from second execution unit add/saturation proce...
- Patent number 7,694,112
- Issue date Apr 6, 2010
- International Business Machines Corporation
- Harry S. Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to reduce power consumption within a clock gated synchronous...
- Patent number 7,639,046
- Issue date Dec 29, 2009
- International Business Machines Corporation
- Tobias Gemmeke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Floating point unit with fused multiply add and method for calculat...
- Patent number 7,461,117
- Issue date Dec 2, 2008
- International Business Machines Corporation
- Son Dao Trong
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Binary Logic Unit and Method to Operate a Binary Logic Unit
- Publication number 20130181743
- Publication date Jul 18, 2013
- International Business Machines Corporation
- Tobias Gemmeke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Zero Indication Forwarding for Floating Point Unit Power Reduction
- Publication number 20120284548
- Publication date Nov 8, 2012
- IBM Corporation
- Harry S. Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REUSE OF ROUNDER FOR FIXED CONVERSION OF LOG INSTRUCTIONS
- Publication number 20100174764
- Publication date Jul 8, 2010
- International Business Machines Corporation
- Maarten Boersma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SHIFTER WITH ALL-ONE AND ALL-ZERO DETECTION
- Publication number 20100146023
- Publication date Jun 10, 2010
- International Business Machines Corporation
- Maarten Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED RESIDUE-CHECKING OF A FLOATING POINT UNIT
- Publication number 20100100578
- Publication date Apr 22, 2010
- International Business Machines Corporation
- Son Trong Dao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST FLOATING POINT COMPARE WITH SLOWER BACKUP FOR CORNER CASES
- Publication number 20100100713
- Publication date Apr 22, 2010
- International Business Machines Corporation
- Maarten J. Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR STORING NUMBERS IN FIRST AND SECOND FORMATS I...
- Publication number 20100095099
- Publication date Apr 15, 2010
- International Business Machines Corporation
- Maarten Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NORMALIZER SHIFT PREDICTION FOR LOG ESTIMATE INSTRUCTIONS
- Publication number 20100063985
- Publication date Mar 11, 2010
- International Business Machines Corporation
- Maarten J. Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING MULTIPLE FORMATS IN A FLOATING POINT PROCESSOR
- Publication number 20100063987
- Publication date Mar 11, 2010
- International Business Machines Corporation
- Maarten J. Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND ELECTRONIC COMPUTING CIRCUIT FOR OPERAND WIDTH REDUCTION...
- Publication number 20100057825
- Publication date Mar 4, 2010
- International Business Machines Corporation
- Tobias Gemmeke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3-Stack Floorplan for Floating Point Unit
- Publication number 20100058266
- Publication date Mar 4, 2010
- International Business Machines Corporation
- Maarten Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT FORCING OF CORNER CASES IN A FLOATING POINT ROUNDER
- Publication number 20100023573
- Publication date Jan 28, 2010
- International Business Machines Corporation
- Maarten J. Boersma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZERO INDICATION FORWARDING FOR FLOATING POINT UNIT POWER REDUCTION
- Publication number 20100017635
- Publication date Jan 21, 2010
- HARRY S. BAROWSKI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR SIGN-EXTENSION IN A MULTI-PRECISION MULTIPLIER
- Publication number 20090198758
- Publication date Aug 6, 2009
- International Business Machines Corporation
- Harry S. Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR CONFLICT-FREE, COOPERATIVE EXECUTION OF COMPUTATIONAL P...
- Publication number 20090198974
- Publication date Aug 6, 2009
- International Business Machines Corporation
- Harry S. Barowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR CHIP WITH A PLURALITY OF SCANNABLE STORAGE ELEMENTS A...
- Publication number 20080276140
- Publication date Nov 6, 2008
- Tobias Gemmeke
- G01 - MEASURING TESTING
Information Patent Application
DESIGN STRUCTURE TO REDUCE POWER CONSUMPTION WITHIN A CLOCK GATED S...
- Publication number 20080169842
- Publication date Jul 17, 2008
- Tobias Gemmeke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD TO REDUCE POWER CONSUMPTION WITHIN A CLOCK GATED SYNCHRONOUS...
- Publication number 20080169841
- Publication date Jul 17, 2008
- Tobias Gemmeke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Binary Logic Unit and Method to Operate a Binary Logic Unit
- Publication number 20080162897
- Publication date Jul 3, 2008
- International Business Machines Corporation
- Tobias Gemmeke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Leading-Zero Counter and Method to Count Leading Zeros
- Publication number 20070050435
- Publication date Mar 1, 2007
- Christian Jacobi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Processor for Performing a Floating-Point Instruction Wi...
- Publication number 20070038693
- Publication date Feb 15, 2007
- Christian Jacobi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Floating point unit with fused multiply add and method for calculat...
- Publication number 20060184601
- Publication date Aug 17, 2006
- Son Dao Trong
- G06 - COMPUTING CALCULATING COUNTING

Jochen Preiss

Person

Patents Grantslast 30 patents

Binary logic unit and method to operate a binary logic unit

Reuse of rounder for fixed conversion of log instructions

Zero indication forwarding for floating point unit power reduction

Distributed residue-checking of a floating point unit

Binary logic unit and method to operate a binary logic unit

Fast floating point compare with slower backup for corner cases

Electronic computing circuit for operand width reduction for a modu...

Efficient forcing of corner cases in a floating point rounder

System and method for storing numbers in first and second formats i...

Shifter with all-one and all-zero detection using a portion of part...

Supporting multiple formats in a floating point processor

Zero indication forwarding for floating point unit power reduction

Normalizer shift prediction for log estimate instructions

3-stack floorplan for floating point unit

Semiconductor chip with a plurality of scannable storage elements a...

Design structure to reduce power consumption within a clock gated s...

Multiplexing output from second execution unit add/saturation proce...

Method to reduce power consumption within a clock gated synchronous...

Floating point unit with fused multiply add and method for calculat...

Patents Applicationslast 30 patents

Binary Logic Unit and Method to Operate a Binary Logic Unit

Zero Indication Forwarding for Floating Point Unit Power Reduction

REUSE OF ROUNDER FOR FIXED CONVERSION OF LOG INSTRUCTIONS

SHIFTER WITH ALL-ONE AND ALL-ZERO DETECTION

DISTRIBUTED RESIDUE-CHECKING OF A FLOATING POINT UNIT

FAST FLOATING POINT COMPARE WITH SLOWER BACKUP FOR CORNER CASES

SYSTEM AND METHOD FOR STORING NUMBERS IN FIRST AND SECOND FORMATS I...

NORMALIZER SHIFT PREDICTION FOR LOG ESTIMATE INSTRUCTIONS

SUPPORTING MULTIPLE FORMATS IN A FLOATING POINT PROCESSOR

METHOD AND ELECTRONIC COMPUTING CIRCUIT FOR OPERAND WIDTH REDUCTION...

3-Stack Floorplan for Floating Point Unit

EFFICIENT FORCING OF CORNER CASES IN A FLOATING POINT ROUNDER

ZERO INDICATION FORWARDING FOR FLOATING POINT UNIT POWER REDUCTION

METHOD FOR SIGN-EXTENSION IN A MULTI-PRECISION MULTIPLIER

METHODS FOR CONFLICT-FREE, COOPERATIVE EXECUTION OF COMPUTATIONAL P...

SEMICONDUCTOR CHIP WITH A PLURALITY OF SCANNABLE STORAGE ELEMENTS A...

DESIGN STRUCTURE TO REDUCE POWER CONSUMPTION WITHIN A CLOCK GATED S...

METHOD TO REDUCE POWER CONSUMPTION WITHIN A CLOCK GATED SYNCHRONOUS...

Binary Logic Unit and Method to Operate a Binary Logic Unit

Leading-Zero Counter and Method to Count Leading Zeros

Method and Processor for Performing a Floating-Point Instruction Wi...

Floating point unit with fused multiply add and method for calculat...