Joel J. Graber

Person

Richardson, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Delay testing capturing second response to first response as stimulus
- Patent number 9,103,886
- Issue date Aug 11, 2015
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scan path delay testing with two memories and three subdivisions
- Patent number 8,683,281
- Issue date Mar 25, 2014
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Memory coupling scan input to first of scan path segments
- Patent number 8,356,220
- Issue date Jan 15, 2013
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Capturing response after simultaneously inputting last stimulus bit...
- Patent number 8,185,789
- Issue date May 22, 2012
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Segmented scan paths with cache bit memory inputs
- Patent number 8,015,464
- Issue date Sep 6, 2011
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Adjusting output buffer timing based on drive strength
- Patent number 7,795,918
- Issue date Sep 14, 2010
- Texas Instruments Incorporated
- Joel J. Graber
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Response bits as stimulus in subdivided scan path delay test
- Patent number 7,437,639
- Issue date Oct 14, 2008
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Programmable built in self test of memory
- Patent number 7,325,178
- Issue date Jan 29, 2008
- Texas Instruments Incorporated
- Raguram Damodaran
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrical fuse control of memory slowdown
- Patent number 7,095,671
- Issue date Aug 22, 2006
- Texas Instruments Incorporated
- Manjeri Krishnan
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrical fuse control of memory slowdown
- Patent number 6,928,011
- Issue date Aug 9, 2005
- Texas Instruments Incorporated
- Manjeri Krishnan
- G11 - INFORMATION STORAGE
Information Patent Grant
IC with cache bit memory in series with scan segment
- Patent number 6,898,749
- Issue date May 24, 2005
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Circuits, systems, and methods for uniquely identifying a microproc...
- Patent number 6,065,113
- Issue date May 16, 2000
- Texas Instruments Incorporated
- Jonathan H. Shiell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuits, systems, and methods for external evaluation of microproc...
- Patent number 6,061,811
- Issue date May 9, 2000
- Texas Instruments Incorporated
- James O. Bondi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS
- Publication number 20140157071
- Publication date Jun 5, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS
- Publication number 20130097468
- Publication date Apr 18, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS
- Publication number 20120204072
- Publication date Aug 9, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
LOW POWER SCAN AND DELAY TEST METHOD AND APPARATUS
- Publication number 20110289371
- Publication date Nov 24, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Adjusting Output Buffer Timing Based on Drive Strength
- Publication number 20090045845
- Publication date Feb 19, 2009
- Joel J. Graber
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS
- Publication number 20080320351
- Publication date Dec 25, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Electrical fuse control of memory slowdown
- Publication number 20050213411
- Publication date Sep 29, 2005
- Manjeri Krishnan
- G11 - INFORMATION STORAGE
Information Patent Application
Low power scan & delay test method and apparatus
- Publication number 20050204228
- Publication date Sep 15, 2005
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
Programmable built in self test of memory
- Publication number 20050172180
- Publication date Aug 4, 2005
- Raguram Damodaran
- G11 - INFORMATION STORAGE
Information Patent Application
Electrical fuse control of memory slowdown
- Publication number 20050024960
- Publication date Feb 3, 2005
- Manjeri Krishnan
- G11 - INFORMATION STORAGE
Information Patent Application
Low power scan & delay test method and apparatus
- Publication number 20020035712
- Publication date Mar 21, 2002
- Lee D. Whetsel
- G01 - MEASURING TESTING

Joel J. Graber

Person

Patents Grantslast 30 patents

Delay testing capturing second response to first response as stimulus

Scan path delay testing with two memories and three subdivisions

Memory coupling scan input to first of scan path segments

Capturing response after simultaneously inputting last stimulus bit...

Segmented scan paths with cache bit memory inputs

Adjusting output buffer timing based on drive strength

Response bits as stimulus in subdivided scan path delay test

Programmable built in self test of memory

Electrical fuse control of memory slowdown

Electrical fuse control of memory slowdown

IC with cache bit memory in series with scan segment

Circuits, systems, and methods for uniquely identifying a microproc...

Circuits, systems, and methods for external evaluation of microproc...

Patents Applicationslast 30 patents

LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS

LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS

LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS

LOW POWER SCAN AND DELAY TEST METHOD AND APPARATUS

Adjusting Output Buffer Timing Based on Drive Strength

LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS

Electrical fuse control of memory slowdown

Low power scan & delay test method and apparatus

Programmable built in self test of memory

Electrical fuse control of memory slowdown

Low power scan & delay test method and apparatus