Joerg Wohlfahrt

Person

Kanagawa-ken, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Reducing memory failures in integrated circuits
- Patent number 7,187,602
- Issue date Mar 6, 2007
- Infineon Technologies Aktiengesellschaft
- Joerg Wohlfahrt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cell signal window testing apparatus
- Patent number 6,999,887
- Issue date Feb 14, 2006
- Infineon Technologies AG
- Norbert Rehm
- G11 - INFORMATION STORAGE
Information Patent Grant
Sensing of memory integrated circuits
- Patent number 6,903,959
- Issue date Jun 7, 2005
- Infineon Technologies Aktiengesellschaft
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Sensing test circuit
- Patent number 6,885,597
- Issue date Apr 26, 2005
- Infineon Technologies Aktiengesellschaft
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Grant
Redundancy in series grouped memory architecture
- Patent number 6,856,560
- Issue date Feb 15, 2005
- Infineon Technologies Aktiengesellschaft
- Norbert Rehm
- G11 - INFORMATION STORAGE
Information Patent Grant
2T2C signal margin test mode using a defined charge and discharge o...
- Patent number 6,826,099
- Issue date Nov 30, 2004
- Infineon Technologies AG
- Hans-Oliver Joachim
- G11 - INFORMATION STORAGE
Information Patent Grant
FeRAM memory device
- Patent number 6,807,084
- Issue date Oct 19, 2004
- Infineon Technologies AG
- Joerg Wohlfahrt
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture with series grouped by cells
- Patent number 6,800,890
- Issue date Oct 5, 2004
- Infineon Technologies Aktiengesellschaft
- Joerg Wohlfahrt
- G11 - INFORMATION STORAGE
Information Patent Grant
Variable capacitances for memory cells within a cell group
- Patent number 6,731,529
- Issue date May 4, 2004
- Infineon Technologies Aktiengesellschaft
- Michael Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
2T2C signal margin test mode using resistive element
- Patent number 6,731,554
- Issue date May 4, 2004
- Infineon Technologies AG
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Grant
Series memory architecture
- Patent number 6,720,598
- Issue date Apr 13, 2004
- Infineon Technologies Aktiengesellschaft
- Joerg Wohlfahrt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for semiconductor yield loss calculation
- Patent number 6,717,431
- Issue date Apr 6, 2004
- Infineon Technologies Richmond, LP
- Dieter Rathei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Historical information storage for integrated circuits
- Patent number 6,707,699
- Issue date Mar 16, 2004
- Infineon Technologies Aktiengesellschaft
- Michael Klaus Jacob
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture
- Patent number 6,639,824
- Issue date Oct 28, 2003
- Infineon Technologies Aktiengesellschaft
- Joerg Wohlfahrt
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Reference circuit implemented to reduce the degradation of referenc...
- Publication number 20050063212
- Publication date Mar 24, 2005
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
Memory cell signal window testing apparatus
- Publication number 20050033541
- Publication date Feb 10, 2005
- Norbert Rehm
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARCHITECTURE WITH SERIES GROUPED BY CELLS
- Publication number 20040232457
- Publication date Nov 25, 2004
- Joerg Wohlfahrt
- G11 - INFORMATION STORAGE
Information Patent Application
FERAM MEMORY DEVICE
- Publication number 20040208043
- Publication date Oct 21, 2004
- Joerg Wohlfahrt
- G11 - INFORMATION STORAGE
Information Patent Application
2T2C Signal margin test mode using a defined charge and discharge o...
- Publication number 20040095819
- Publication date May 20, 2004
- Hans-Oliver Joachim
- G11 - INFORMATION STORAGE
Information Patent Application
2T2C SIGNAL MARGIN TEST MODE USING RESISTIVE ELEMENT
- Publication number 20040095820
- Publication date May 20, 2004
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
2T2C signal margin test mode using different pre-charge levels for...
- Publication number 20040095799
- Publication date May 20, 2004
- Michael Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
Ferroelectric memory architecture
- Publication number 20040095798
- Publication date May 20, 2004
- Joerg Wohlfahrt
- G11 - INFORMATION STORAGE
Information Patent Application
HISTORICAL INFORMATION STORAGE FOR INTEGRATED CIRCUITS
- Publication number 20040057273
- Publication date Mar 25, 2004
- Michael Klaus Jacob
- G11 - INFORMATION STORAGE
Information Patent Application
SERIES MEMORY ARCHITECTURE
- Publication number 20040056287
- Publication date Mar 25, 2004
- Joerg Wohlfahrt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SENSING OF MEMORY INTEGRATED CIRCUITS
- Publication number 20040057275
- Publication date Mar 25, 2004
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
Sensing test circuit
- Publication number 20040047171
- Publication date Mar 11, 2004
- Thomas Roehr
- G11 - INFORMATION STORAGE
Information Patent Application
Variable capacitances for memory cells within a cell group
- Publication number 20030223263
- Publication date Dec 4, 2003
- Michael Jacob
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for semiconductor yield loss calculation
- Publication number 20030207474
- Publication date Nov 6, 2003
- Infineon Technologies North America Corp.
- Dieter Rathei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Redundancy in chained memory architectures
- Publication number 20030202386
- Publication date Oct 30, 2003
- Norbert Rehm
- G11 - INFORMATION STORAGE
Information Patent Application
Reducing Memory Failures in Integrated Circuits
- Publication number 20030179616
- Publication date Sep 25, 2003
- Joerg Wohlfahrt
- G06 - COMPUTING CALCULATING COUNTING

Joerg Wohlfahrt

Person

Patents Grantslast 30 patents

Reducing memory failures in integrated circuits

Memory cell signal window testing apparatus

Sensing of memory integrated circuits

Sensing test circuit

Redundancy in series grouped memory architecture

2T2C signal margin test mode using a defined charge and discharge o...

FeRAM memory device

Memory architecture with series grouped by cells

Variable capacitances for memory cells within a cell group

2T2C signal margin test mode using resistive element

Series memory architecture

Method for semiconductor yield loss calculation

Historical information storage for integrated circuits

Memory architecture

Patents Applicationslast 30 patents

Reference circuit implemented to reduce the degradation of referenc...

Memory cell signal window testing apparatus

MEMORY ARCHITECTURE WITH SERIES GROUPED BY CELLS

FERAM MEMORY DEVICE

2T2C Signal margin test mode using a defined charge and discharge o...

2T2C SIGNAL MARGIN TEST MODE USING RESISTIVE ELEMENT

2T2C signal margin test mode using different pre-charge levels for...

Ferroelectric memory architecture

HISTORICAL INFORMATION STORAGE FOR INTEGRATED CIRCUITS

SERIES MEMORY ARCHITECTURE

SENSING OF MEMORY INTEGRATED CIRCUITS

Sensing test circuit

Variable capacitances for memory cells within a cell group

Method for semiconductor yield loss calculation

Redundancy in chained memory architectures

Reducing Memory Failures in Integrated Circuits