Johann Pfeiffer

Person

Ottobrunn, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Memory module with test structure
- Patent number 7,428,671
- Issue date Sep 23, 2008
- Qimonda AG
- Johann Pfeiffer
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and auxiliary device for testing a RAM memory circuit
- Patent number 7,278,072
- Issue date Oct 2, 2007
- Infineon Technologies AG
- Johann Pfeiffer
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated semiconductor memory with redundant memory cells replace...
- Patent number 7,236,412
- Issue date Jun 26, 2007
- Infineon Technologies AG
- Manfred Pröll
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with a test circuit
- Patent number 7,135,723
- Issue date Nov 14, 2006
- Infineon Technologies AG
- Kazimierz Szczpinski
- G01 - MEASURING TESTING
Information Patent Grant
Memory having internal column counter for compression test mode
- Patent number 7,123,542
- Issue date Oct 17, 2006
- Infineon Technologies AG
- Khaled Fekih-Romdhane
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit device with clock pulse detection facility
- Patent number 7,068,079
- Issue date Jun 27, 2006
- Infineon Technologies AG
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital memory circuit having a plurality of memory banks
- Patent number 7,064,999
- Issue date Jun 20, 2006
- Infineon Technologies AG
- Helmut Fischer
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor circuit and initialization method
- Patent number 6,989,707
- Issue date Jan 24, 2006
- Infineon Technologies AG
- Graf Albert Von Keyserlingk
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing the current consumption of an ele...
- Patent number 6,986,088
- Issue date Jan 10, 2006
- Infineon Technologies AG
- Helmut Fischer
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated module having a delay element
- Patent number 6,975,131
- Issue date Dec 13, 2005
- Infineon Technologies AG
- Kazimierz Szczypinski
- G01 - MEASURING TESTING
Information Patent Grant
RAM memory circuit having a plurality of banks and an auxiliary dev...
- Patent number 6,961,273
- Issue date Nov 1, 2005
- Infineon Technologies AG
- Sven Boldt
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory with address decoding unit, and address loadin...
- Patent number 6,937,537
- Issue date Aug 30, 2005
- Infineon Technologies AG
- Johann Pfeiffer
- G11 - INFORMATION STORAGE
Information Patent Grant
RAM memory circuit and method for memory operation at a multiplied...
- Patent number 6,928,024
- Issue date Aug 9, 2005
- Infineon Technologies AG
- Johann Pfeiffer
- G11 - INFORMATION STORAGE
Information Patent Grant
Semi-conductor component with clock relaying device
- Patent number 6,917,562
- Issue date Jul 12, 2005
- Infineon Technologies AG
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated memory
- Patent number 6,917,563
- Issue date Jul 12, 2005
- Infineon Technologies AG
- Reidar Lindstedt
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory element with direct connection of the I/Os to...
- Patent number 6,914,796
- Issue date Jul 5, 2005
- Infineon Technologies AG
- Andrea Zuckerstatter
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for writing and reading data from a dynamic memo...
- Patent number 6,859,411
- Issue date Feb 22, 2005
- Infineon Technologies AG
- Johann Pfeiffer
- G11 - INFORMATION STORAGE
Information Patent Grant
RAM memory circuit and method for controlling the same
- Patent number 6,822,923
- Issue date Nov 23, 2004
- Infineon Technologies AG
- Johann Pfeiffer
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory and method for operating the semiconductor memory
- Patent number 6,738,309
- Issue date May 18, 2004
- Infineon Technologies AG
- Alexander Benedix
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit for an electronic semiconductor module
- Patent number 6,731,131
- Issue date May 4, 2004
- Infineon Technologies AG
- Johann Pfeiffer
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital memory circuit having a plurality of segmented memory areas
- Patent number 6,711,085
- Issue date Mar 23, 2004
- Infineon Technologies AG
- Helmut Fischer
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital memory circuit having a plurality of memory areas
- Patent number 6,711,072
- Issue date Mar 23, 2004
- Infineon Technologies AG
- Helmut Fischer
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit having a plurality of memory areas
- Patent number 6,636,453
- Issue date Oct 21, 2003
- Infineon Technologies AG
- Helmut Fischer
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Memory having internal column counter for compression test mode
- Publication number 20060133187
- Publication date Jun 22, 2006
- Khaled Fekih-Romdhane
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated semiconductor memory having redundant memory cells
- Publication number 20050174863
- Publication date Aug 11, 2005
- Manfred Proll
- G11 - INFORMATION STORAGE
Information Patent Application
RAM memory circuit having a plurality of banks and an auxiliary dev...
- Publication number 20050152194
- Publication date Jul 14, 2005
- Sven Boldt
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit having a voltage monitoring circuit and a method...
- Publication number 20040263216
- Publication date Dec 30, 2004
- Manfred Proll
- G01 - MEASURING TESTING
Information Patent Application
Integrated module having a delay element
- Publication number 20040222811
- Publication date Nov 11, 2004
- Kazimierz Szczypinski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Integrated circuit with a test circuit
- Publication number 20040217349
- Publication date Nov 4, 2004
- Kazimierz Szczpinski
- G01 - MEASURING TESTING
Information Patent Application
Memory module with test structure
- Publication number 20040153922
- Publication date Aug 5, 2004
- Johann Pfeiffer
- G11 - INFORMATION STORAGE
Information Patent Application
Semi-conductor component with clock relaying device
- Publication number 20040124886
- Publication date Jul 1, 2004
- Infineon Technologies AG
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit device with clock pulse detection facility
- Publication number 20040124887
- Publication date Jul 1, 2004
- Andre Schaefer
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated memory
- Publication number 20040109359
- Publication date Jun 10, 2004
- Reidar Lindstedt
- G11 - INFORMATION STORAGE
Information Patent Application
Digital memory circuit having a plurality of memory banks
- Publication number 20040088613
- Publication date May 6, 2004
- Helmut Fischer
- G11 - INFORMATION STORAGE
Information Patent Application
RAM memory circuit and method for memory operation at a multiplied...
- Publication number 20040076040
- Publication date Apr 22, 2004
- Johann Pfeiffer
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit and method for writing and reading data from a dynamic memo...
- Publication number 20040027975
- Publication date Feb 12, 2004
- Johann Pfeiffer
- G11 - INFORMATION STORAGE
Information Patent Application
RAM memory circuit and method for controlling the same
- Publication number 20040008548
- Publication date Jan 15, 2004
- Johann Pfeiffer
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory with address decoding unit, and address loadin...
- Publication number 20030231535
- Publication date Dec 18, 2003
- Johann Pfeiffer
- G11 - INFORMATION STORAGE
Information Patent Application
Method and auxiliary device for testing a RAM memory circuit
- Publication number 20030217313
- Publication date Nov 20, 2003
- Johann Pfeiffer
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit configuration and method for transmitting digital signals
- Publication number 20030215008
- Publication date Nov 20, 2003
- Konstantin Korotkov
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Semiconductor circuit and initialization method
- Publication number 20030197545
- Publication date Oct 23, 2003
- Graf Albert Von Keyserlingk
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for reducing the current consumption of an ele...
- Publication number 20030102881
- Publication date Jun 5, 2003
- Helmut Fischer
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit for an electronic semiconductor module
- Publication number 20030080336
- Publication date May 1, 2003
- Johann Pfeiffer
- G11 - INFORMATION STORAGE
Information Patent Application
Digital memory circuit having a plurality of segmented memory areas
- Publication number 20030067820
- Publication date Apr 10, 2003
- Helmut Fischer
- G11 - INFORMATION STORAGE
Information Patent Application
Digital memory circuit having a plurality of memory areas
- Publication number 20030067821
- Publication date Apr 10, 2003
- Helmut Fischer
- G11 - INFORMATION STORAGE
Information Patent Application
Method for accessing memory cells of a DRAM memory module
- Publication number 20030043654
- Publication date Mar 6, 2003
- Johann Pfeiffer
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory and method for operating the semiconductor memory
- Publication number 20020176316
- Publication date Nov 28, 2002
- Alexander Benedix
- G11 - INFORMATION STORAGE
Information Patent Application
Memory circuit having a plurality of memory areas
- Publication number 20020163849
- Publication date Nov 7, 2002
- Helmut Fischer
- G11 - INFORMATION STORAGE

Johann Pfeiffer

Person

Patents Grantslast 30 patents

Memory module with test structure

Method and auxiliary device for testing a RAM memory circuit

Integrated semiconductor memory with redundant memory cells replace...

Integrated circuit with a test circuit

Memory having internal column counter for compression test mode

Circuit device with clock pulse detection facility

Digital memory circuit having a plurality of memory banks

Semiconductor circuit and initialization method

Method and apparatus for reducing the current consumption of an ele...

Integrated module having a delay element

RAM memory circuit having a plurality of banks and an auxiliary dev...

Semiconductor memory with address decoding unit, and address loadin...

RAM memory circuit and method for memory operation at a multiplied...

Semi-conductor component with clock relaying device

Integrated memory

Semiconductor memory element with direct connection of the I/Os to...

Circuit and method for writing and reading data from a dynamic memo...

RAM memory circuit and method for controlling the same

Semiconductor memory and method for operating the semiconductor memory

Circuit for an electronic semiconductor module

Digital memory circuit having a plurality of segmented memory areas

Digital memory circuit having a plurality of memory areas

Memory circuit having a plurality of memory areas

Patents Applicationslast 30 patents

Memory having internal column counter for compression test mode

Integrated semiconductor memory having redundant memory cells

RAM memory circuit having a plurality of banks and an auxiliary dev...

Integrated circuit having a voltage monitoring circuit and a method...

Integrated module having a delay element

Integrated circuit with a test circuit

Memory module with test structure

Semi-conductor component with clock relaying device

Circuit device with clock pulse detection facility

Integrated memory

Digital memory circuit having a plurality of memory banks

RAM memory circuit and method for memory operation at a multiplied...

Circuit and method for writing and reading data from a dynamic memo...

RAM memory circuit and method for controlling the same

Semiconductor memory with address decoding unit, and address loadin...

Method and auxiliary device for testing a RAM memory circuit

Circuit configuration and method for transmitting digital signals

Semiconductor circuit and initialization method

Method and apparatus for reducing the current consumption of an ele...

Circuit for an electronic semiconductor module

Digital memory circuit having a plurality of segmented memory areas

Digital memory circuit having a plurality of memory areas

Method for accessing memory cells of a DRAM memory module

Semiconductor memory and method for operating the semiconductor memory

Memory circuit having a plurality of memory areas