John Apostol

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit with low power mode management
- Patent number 12,132,386
- Issue date Oct 29, 2024
- Texas Instruments Incorporated
- Venkateswar Kowkutla
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Technique for clock alignment supporting reset isolation
- Patent number 12,072,731
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Varun Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System on a chip with an integrated configurable safety master micr...
- Patent number 11,899,563
- Issue date Feb 13, 2024
- Texas Instruments Incorporated
- Venkateswar Kowkutla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Technique for clock alignment supporting reset isolation
- Patent number 11,662,763
- Issue date May 30, 2023
- Texas Instruments Incorporated
- Varun Singh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accurate noise modeling in digital designs
- Patent number 7,363,604
- Issue date Apr 22, 2008
- Texas Instruments Incorporated
- Anthony M. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell-based noise characterization and evaluation
- Patent number 6,732,339
- Issue date May 4, 2004
- Texas Instruments Incorporated
- Nagaraj N. Savithri
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell-based noise characterization and evaluation
- Patent number 6,493,853
- Issue date Dec 10, 2002
- Texas Instruments Incorporated
- Nagaraj N. Savithri
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT WITH LOW POWER MODE MANAGEMENT
- Publication number 20250015698
- Publication date Jan 9, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Venkateswar Kowkutla
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
SYSTEM ON A CHIP WITH AN INTEGRATED CONFIGURABLE SAFETY MASTER MICR...
- Publication number 20240134776
- Publication date Apr 25, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Venkateswar Kowkutla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE FOR CLOCK ALIGNMENT SUPPORTING RESET ISOLATION
- Publication number 20230280784
- Publication date Sep 7, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Varun SINGH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH LOW POWER MODE MANAGEMENT
- Publication number 20230238872
- Publication date Jul 27, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Venkateswar Kowkutla
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
POWER-ON-RESET SIGNAL ISOLATION DURING LOWER POWER MODE
- Publication number 20230205305
- Publication date Jun 29, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Venkateswar Kowkutla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM ON A CHIP WITH AN INTEGRATED CONFIGURABLE SAFETY MASTER MICR...
- Publication number 20230205672
- Publication date Jun 29, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Venkateswar Kowkutla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUE FOR CLOCK ALIGNMENT SUPPORTING RESET ISOLATION
- Publication number 20230168709
- Publication date Jun 1, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Varun SINGH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Accurate noise modeling in digital designs
- Publication number 20070079265
- Publication date Apr 5, 2007
- Anthony M. Hill
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cell-based noise characterization and evaluation
- Publication number 20030079191
- Publication date Apr 24, 2003
- Nagaraj N. Savithri
- G06 - COMPUTING CALCULATING COUNTING

John Apostol

Person

Patents Grantslast 30 patents

Integrated circuit with low power mode management

Technique for clock alignment supporting reset isolation

System on a chip with an integrated configurable safety master micr...

Technique for clock alignment supporting reset isolation

Accurate noise modeling in digital designs

Cell-based noise characterization and evaluation

Cell-based noise characterization and evaluation

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT WITH LOW POWER MODE MANAGEMENT

SYSTEM ON A CHIP WITH AN INTEGRATED CONFIGURABLE SAFETY MASTER MICR...

TECHNIQUE FOR CLOCK ALIGNMENT SUPPORTING RESET ISOLATION

INTEGRATED CIRCUIT WITH LOW POWER MODE MANAGEMENT

POWER-ON-RESET SIGNAL ISOLATION DURING LOWER POWER MODE

SYSTEM ON A CHIP WITH AN INTEGRATED CONFIGURABLE SAFETY MASTER MICR...

TECHNIQUE FOR CLOCK ALIGNMENT SUPPORTING RESET ISOLATION

Accurate noise modeling in digital designs

Cell-based noise characterization and evaluation