John B. HALBERT

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Stacked memory with interface providing offset interconnects
- Patent number 12,046,577
- Issue date Jul 23, 2024
- Tahoe Research, LTD.
- Pete D. Vogt
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with reduced exposure to manufacturing related data corrupti...
- Patent number 11,010,304
- Issue date May 18, 2021
- Intel Corporation
- Uksong Kang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-die ECC with error counter and internal address generation
- Patent number 10,949,296
- Issue date Mar 16, 2021
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device error check and scrub mode and error transparency
- Patent number 10,810,079
- Issue date Oct 20, 2020
- Intel Corporation
- John B Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Targeted aliasing single error correction (SEC) code
- Patent number 10,572,343
- Issue date Feb 25, 2020
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performance of additional refresh operations during self-refresh mode
- Patent number 10,522,207
- Issue date Dec 31, 2019
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Extracting selective information from on-die dynamic random access...
- Patent number 10,496,473
- Issue date Dec 3, 2019
- Intel Corporation
- Debaleena Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible command addressing for memory
- Patent number 10,489,083
- Issue date Nov 26, 2019
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stacked memory chip device with enhanced data protection capability
- Patent number 10,459,809
- Issue date Oct 29, 2019
- Intel Corporation
- Hussein Alameer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduction of power consumption in memory devices during refresh modes
- Patent number 10,242,727
- Issue date Mar 26, 2019
- Intel Corporation
- Christopher E. Cox
- G11 - INFORMATION STORAGE
Information Patent Grant
Row hammer refresh command
- Patent number 10,210,925
- Issue date Feb 19, 2019
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device error check and scrub mode and error transparency
- Patent number 10,127,101
- Issue date Nov 13, 2018
- Intel Corporation
- John B Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, method and system for performing successive writes to a...
- Patent number 10,121,532
- Issue date Nov 6, 2018
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Validation of memory on-die error correction code
- Patent number 10,108,512
- Issue date Oct 23, 2018
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Precharging and refreshing banks in memory device with bank group a...
- Patent number 10,109,340
- Issue date Oct 23, 2018
- Intel Corporation
- Kuljit S Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Row hammer monitoring based on stored row hammer threshold value
- Patent number 10,083,737
- Issue date Sep 25, 2018
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduction of power consumption in memory devices during refresh modes
- Patent number 9,984,737
- Issue date May 29, 2018
- Intel Corporation
- Christopher E. Cox
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller-controlled refresh abort
- Patent number 9,953,694
- Issue date Apr 24, 2018
- Intel Corporation
- Bruce Querbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Device, system and method to restrict access to data error information
- Patent number 9,904,591
- Issue date Feb 27, 2018
- Intel Corporation
- John B Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Row hammer refresh command
- Patent number 9,865,326
- Issue date Jan 9, 2018
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device check bit read mode
- Patent number 9,842,021
- Issue date Dec 12, 2017
- Intel Corporation
- John B Halbert
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory refresh operation with page open
- Patent number 9,824,743
- Issue date Nov 21, 2017
- Intel Corporation
- Bruce Querbach
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device on-die error checking and correcting code
- Patent number 9,817,714
- Issue date Nov 14, 2017
- Intel Corporation
- John B Halbert
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Extracting selective information from on-die dynamic random access...
- Patent number 9,811,420
- Issue date Nov 7, 2017
- Intel Corporation
- Debaleena Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stacked memory with interface providing offset interconnects
- Patent number 9,768,148
- Issue date Sep 19, 2017
- Intel Corporation
- Pete Vogt
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, apparatus and system for responding to a row hammer event
- Patent number 9,761,298
- Issue date Sep 12, 2017
- Intel Corporation
- John B. Halbert
- G11 - INFORMATION STORAGE
Information Patent Grant
Row hammer refresh command
- Patent number 9,747,971
- Issue date Aug 29, 2017
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
On-die ECC with error counter and internal address generation
- Patent number 9,740,558
- Issue date Aug 22, 2017
- Intel Corporation
- John B. Halbert
- G11 - INFORMATION STORAGE
Information Patent Grant
Precharging and refreshing banks in memory device with bank group a...
- Patent number 9,728,245
- Issue date Aug 8, 2017
- Intel Corporation
- Kuljit S Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Performance of additional refresh operations during self-refresh mode
- Patent number 9,721,640
- Issue date Aug 1, 2017
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS
- Publication number 20240379625
- Publication date Nov 14, 2024
- Tahoe Research, Ltd.
- Pete D. VOGT
- G11 - INFORMATION STORAGE
Information Patent Application
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS
- Publication number 20190304953
- Publication date Oct 3, 2019
- Intel Corporation
- Pete D. VOGT
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CHIP HAVING REDUCED BASELINE REFRESH RATE WITH ADDITIONAL RE...
- Publication number 20190096472
- Publication date Mar 28, 2019
- Uksong KANG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE ERROR CHECK AND SCRUB MODE AND ERROR TRANSPARENCY
- Publication number 20190073261
- Publication date Mar 7, 2019
- Intel Corporation
- John B. HALBERT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY WITH REDUCED EXPOSURE TO MANUFACTURING RELATED DATA CORRUPTI...
- Publication number 20190042449
- Publication date Feb 7, 2019
- Intel Corporation
- Uksong KANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STACKED MEMORY CHIP DEVICE WITH ENHANCED DATA PROTECTION CAPABILITY
- Publication number 20190004909
- Publication date Jan 3, 2019
- Intel Corporation
- Hussein ALAMEER
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCTION OF POWER CONSUMPTION IN MEMORY DEVICES DURING REFRESH MODES
- Publication number 20180336943
- Publication date Nov 22, 2018
- Intel Corporation
- Christopher E. COX
- G11 - INFORMATION STORAGE
Information Patent Application
TARGETED ALIASING SINGLE ERROR CORRECTION (SEC) CODE
- Publication number 20180203761
- Publication date Jul 19, 2018
- Intel Corporation
- John B. HALBERT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROW HAMMER REFRESH COMMAND
- Publication number 20180174639
- Publication date Jun 21, 2018
- Intel Corporation
- Kuljit S Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREASED REDUNDANCY IN MULTI-DEVICE MEMORY PACKAGE TO IMPROVE RELI...
- Publication number 20180137005
- Publication date May 17, 2018
- Intel Corporation
- Wei Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STACKED MEMORY WITH INTERFACE PROVIDING OFFSET Interconnect S
- Publication number 20180122779
- Publication date May 3, 2018
- Pete D. VOGT
- G11 - INFORMATION STORAGE
Information Patent Application
STAGGERING INITIATION OF REFRESH IN A GROUP OF MEMORY DEVICES
- Publication number 20180096719
- Publication date Apr 5, 2018
- Intel Corporation
- Shigeki TOMISHIMA
- G11 - INFORMATION STORAGE
Information Patent Application
Performance of Additional Refresh Operations During Self-Refresh Mode
- Publication number 20180047439
- Publication date Feb 15, 2018
- Intel Corporation
- Kuljit S. BAINS
- G11 - INFORMATION STORAGE
Information Patent Application
PRECHARGING AND REFRESHING BANKS IN MEMORY DEVICE WITH BANK GROUP A...
- Publication number 20180025773
- Publication date Jan 25, 2018
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Application
EXTRACTING SELECTIVE INFORMATION FROM ON-DIE DYNAMIC RANDOM ACCESS...
- Publication number 20180024878
- Publication date Jan 25, 2018
- Intel Corporation
- Debaleena Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROW HAMMER MONITORING BASED ON STORED ROW HAMMER THRESHOLD VALUE
- Publication number 20170365324
- Publication date Dec 21, 2017
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS, METHOD AND SYSTEM FOR PERFORMING SUCCESSIVE WRITES TO A...
- Publication number 20170365329
- Publication date Dec 21, 2017
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CONTROLLER-CONTROLLED REFRESH ABORT
- Publication number 20170352406
- Publication date Dec 7, 2017
- Intel Corporation
- Bruce QUERBACH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-DIE ECC WITH ERROR COUNTER AND INTERNAL ADDRESS GENERATION
- Publication number 20170344424
- Publication date Nov 30, 2017
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FLEXIBLE COMMAND ADDRESSING FOR MEMORY
- Publication number 20170300270
- Publication date Oct 19, 2017
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VALIDATION OF MEMORY ON-DIE ERROR CORRECTION CODE
- Publication number 20170286197
- Publication date Oct 5, 2017
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY REFRESH OPERATION WITH PAGE OPEN
- Publication number 20170236575
- Publication date Aug 17, 2017
- Intel Corporation
- Bruce QUERBACH
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCTION OF POWER CONSUMPTION IN MEMORY DEVICES DURING REFRESH MODES
- Publication number 20170169881
- Publication date Jun 15, 2017
- Intel Corporation
- Christopher E. COX
- G11 - INFORMATION STORAGE
Information Patent Application
Performance of Additional Refresh Operations During Self-Refresh Mode
- Publication number 20170169880
- Publication date Jun 15, 2017
- Intel Corporation
- Kuljit S. BAINS
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD, APPARATUS AND SYSTEM TO MANAGE IMPLICIT PRE-CHARGE COMMAND...
- Publication number 20170140801
- Publication date May 18, 2017
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR RESPONDING TO A ROW HAMMER EVENT
- Publication number 20170092350
- Publication date Mar 30, 2017
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ROW HAMMER REFRESH COMMAND
- Publication number 20170076779
- Publication date Mar 16, 2017
- Intel Corporation
- Kuljit S Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE ON-DIE ERROR CHECKING AND CORRECTING CODE
- Publication number 20170063394
- Publication date Mar 2, 2017
- Intel Corporation
- John B. Halbert
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Memory device check bit read mode
- Publication number 20170060680
- Publication date Mar 2, 2017
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory device error check and scrub mode and error transparency
- Publication number 20170060681
- Publication date Mar 2, 2017
- Intel Corporation
- John B. Halbert
- G06 - COMPUTING CALCULATING COUNTING

John B. HALBERT

Person

Patents Grantslast 30 patents

Stacked memory with interface providing offset interconnects

Memory with reduced exposure to manufacturing related data corrupti...

On-die ECC with error counter and internal address generation

Memory device error check and scrub mode and error transparency

Targeted aliasing single error correction (SEC) code

Performance of additional refresh operations during self-refresh mode

Extracting selective information from on-die dynamic random access...

Flexible command addressing for memory

Stacked memory chip device with enhanced data protection capability

Reduction of power consumption in memory devices during refresh modes

Row hammer refresh command

Memory device error check and scrub mode and error transparency

Apparatus, method and system for performing successive writes to a...

Validation of memory on-die error correction code

Precharging and refreshing banks in memory device with bank group a...

Row hammer monitoring based on stored row hammer threshold value

Reduction of power consumption in memory devices during refresh modes

Memory controller-controlled refresh abort

Device, system and method to restrict access to data error information

Row hammer refresh command

Memory device check bit read mode

Memory refresh operation with page open

Memory device on-die error checking and correcting code

Extracting selective information from on-die dynamic random access...

Stacked memory with interface providing offset interconnects

Method, apparatus and system for responding to a row hammer event

Row hammer refresh command

On-die ECC with error counter and internal address generation

Precharging and refreshing banks in memory device with bank group a...

Performance of additional refresh operations during self-refresh mode

Patents Applicationslast 30 patents

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET INTERCONNECTS

MEMORY CHIP HAVING REDUCED BASELINE REFRESH RATE WITH ADDITIONAL RE...

MEMORY DEVICE ERROR CHECK AND SCRUB MODE AND ERROR TRANSPARENCY

MEMORY WITH REDUCED EXPOSURE TO MANUFACTURING RELATED DATA CORRUPTI...

STACKED MEMORY CHIP DEVICE WITH ENHANCED DATA PROTECTION CAPABILITY

REDUCTION OF POWER CONSUMPTION IN MEMORY DEVICES DURING REFRESH MODES

TARGETED ALIASING SINGLE ERROR CORRECTION (SEC) CODE

ROW HAMMER REFRESH COMMAND

INCREASED REDUNDANCY IN MULTI-DEVICE MEMORY PACKAGE TO IMPROVE RELI...

STACKED MEMORY WITH INTERFACE PROVIDING OFFSET Interconnect S

STAGGERING INITIATION OF REFRESH IN A GROUP OF MEMORY DEVICES

Performance of Additional Refresh Operations During Self-Refresh Mode

PRECHARGING AND REFRESHING BANKS IN MEMORY DEVICE WITH BANK GROUP A...

EXTRACTING SELECTIVE INFORMATION FROM ON-DIE DYNAMIC RANDOM ACCESS...

ROW HAMMER MONITORING BASED ON STORED ROW HAMMER THRESHOLD VALUE

APPARATUS, METHOD AND SYSTEM FOR PERFORMING SUCCESSIVE WRITES TO A...

MEMORY CONTROLLER-CONTROLLED REFRESH ABORT

ON-DIE ECC WITH ERROR COUNTER AND INTERNAL ADDRESS GENERATION

FLEXIBLE COMMAND ADDRESSING FOR MEMORY

VALIDATION OF MEMORY ON-DIE ERROR CORRECTION CODE

MEMORY REFRESH OPERATION WITH PAGE OPEN

REDUCTION OF POWER CONSUMPTION IN MEMORY DEVICES DURING REFRESH MODES

Performance of Additional Refresh Operations During Self-Refresh Mode

METHOD, APPARATUS AND SYSTEM TO MANAGE IMPLICIT PRE-CHARGE COMMAND...

METHOD, APPARATUS AND SYSTEM FOR RESPONDING TO A ROW HAMMER EVENT

ROW HAMMER REFRESH COMMAND

MEMORY DEVICE ON-DIE ERROR CHECKING AND CORRECTING CODE

Memory device check bit read mode

Memory device error check and scrub mode and error transparency