John Christopher Kriz

Person

Palmerton, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Hybrid impedance compensation in a buffer circuit
- Patent number 8,598,941
- Issue date Dec 3, 2013
- LSI Corporation
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Voltage level translator circuit
- Patent number 8,536,925
- Issue date Sep 17, 2013
- Agere Systems LLC
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Current-mode logic buffer with enhanced output swing
- Patent number 8,441,281
- Issue date May 14, 2013
- LSI Corporation
- Makeshwar Kothandaraman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Mode latching buffer circuit
- Patent number 8,362,803
- Issue date Jan 29, 2013
- LSI Corporation
- Peter J. Nicholas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Impedance compensation in a buffer circuit
- Patent number 8,159,262
- Issue date Apr 17, 2012
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interfacing between differing voltage level requirements in an inte...
- Patent number 8,130,030
- Issue date Mar 6, 2012
- LSI Corporation
- Pankaj Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bias voltage generation to protect input/output (IO) circuits durin...
- Patent number 8,125,267
- Issue date Feb 28, 2012
- LSI Corporation
- Pankaj Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Electrostatic discharge protection circuit
- Patent number 8,089,739
- Issue date Jan 3, 2012
- Agere Systems Inc.
- Dipankar Bhattacharya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
I/O buffer with low voltage semiconductor devices
- Patent number 7,936,209
- Issue date May 3, 2011
- LSI Corporation
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bias circuit scheme for improved reliability in high voltage supply...
- Patent number 7,902,904
- Issue date Mar 8, 2011
- LSI Corporation
- Pankaj Kumar
- G05 - CONTROLLING REGULATING
Information Patent Grant
Floating well circuit operable in a failsafe condition and a tolera...
- Patent number 7,876,132
- Issue date Jan 25, 2011
- LSI Corporation
- Pankaj Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory device control for self-refresh mode
- Patent number 7,869,300
- Issue date Jan 11, 2011
- Agere Systems Inc.
- Dharmeshkumar N. Bhakta
- G11 - INFORMATION STORAGE
Information Patent Grant
Multiple-mode compensated buffer circuit
- Patent number 7,642,807
- Issue date Jan 5, 2010
- Agere Systems Inc.
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Enhanced output impedance compensation
- Patent number 7,551,020
- Issue date Jun 23, 2009
- Agere Systems Inc.
- Dipankar Bhattacharya
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Circuit for selectively bypassing a capacitive element
- Patent number 7,529,071
- Issue date May 5, 2009
- Agere Systems Inc.
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power pin to power pin electro-static discharge (ESD) clamp
- Patent number 7,529,070
- Issue date May 5, 2009
- Agere Systems Inc.
- Dipankar Bhattacharya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for improving reliability of an integrated cir...
- Patent number 7,511,550
- Issue date Mar 31, 2009
- Agere Systems Inc.
- Dipankar Bhattacharya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buffer circuit having multiplexed voltage level translation
- Patent number 7,498,860
- Issue date Mar 3, 2009
- Agere Systems Inc.
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Electrostatic discharge protection in a semiconductor device
- Patent number 7,495,873
- Issue date Feb 24, 2009
- Agere Systems Inc.
- Dipankar Bhattacharya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit having enhanced input signal range
- Patent number 7,432,762
- Issue date Oct 7, 2008
- Agere Systems Inc.
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Buffer circuit with enhanced overvoltage protection
- Patent number 7,430,100
- Issue date Sep 30, 2008
- Agere Systems Inc.
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Voltage level translator circuit with wide supply voltage range
- Patent number 7,397,279
- Issue date Jul 8, 2008
- Agere Systems Inc.
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Comparator circuit having reduced pulse width distortion
- Patent number 7,391,825
- Issue date Jun 24, 2008
- Agere Systems Inc.
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Buffer circuit with multiple voltage range
- Patent number 7,382,168
- Issue date Jun 3, 2008
- Agere Systems Inc.
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Floating well circuit having enhanced latch-up performance
- Patent number 7,276,957
- Issue date Oct 2, 2007
- Agere Systems Inc.
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Buffer circuit with current limiting
- Patent number 7,271,614
- Issue date Sep 18, 2007
- Agere Systems Inc.
- Samuel Khoo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Differential buffer circuit with reduced output common mode variation
- Patent number 7,248,079
- Issue date Jul 24, 2007
- Agere Systems Inc.
- Dipankar Bhattacharya
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Reference compensation circuit
- Patent number 7,218,169
- Issue date May 15, 2007
- Agere Syatems Inc.
- Dipankar Bhattacharya
- G05 - CONTROLLING REGULATING
Information Patent Grant
Programmable reset signal that is independent of supply voltage ram...
- Patent number 7,196,561
- Issue date Mar 27, 2007
- Agere Systems Inc.
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Output buffer with selectable slew rate
- Patent number 7,170,324
- Issue date Jan 30, 2007
- Agere Systems Inc.
- Carol Ann Huber
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Current-Mode Logic Buffer with Enhanced Output Swing
- Publication number 20120326745
- Publication date Dec 27, 2012
- LSI Corporation
- Makeshwar Kothandaraman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Hybrid Impedance Compensation in a Buffer Circuit
- Publication number 20120326768
- Publication date Dec 27, 2012
- LSI Corporation
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Mode Latching Buffer Circuit
- Publication number 20120212256
- Publication date Aug 23, 2012
- LSI Corporation
- Peter J. Nicholas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTERFACING BETWEEN DIFFERING VOLTAGE LEVEL REQUIREMENTS IN AN INTE...
- Publication number 20110102045
- Publication date May 5, 2011
- PANKAJ KUMAR
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Interfacing between differing voltage level requirements in an inte...
- Publication number 20110102046
- Publication date May 5, 2011
- PANKAJ KUMAR
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
BIAS VOLTAGE GENERATION TO PROTECT INPUT/OUTPUT (IO) CIRCUITS DURIN...
- Publication number 20110102048
- Publication date May 5, 2011
- LSI Corporation
- Pankaj Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY DEVICE CONTROL FOR SELF-REFRESH MODE
- Publication number 20100278000
- Publication date Nov 4, 2010
- LSI Corporation
- Dharmeshkumar N. Bhakta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
I/O Buffer with Low Voltage Semiconductor Devices
- Publication number 20100271118
- Publication date Oct 28, 2010
- LSI CORPORATION
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Electrostatic Discharge Protection Circuit
- Publication number 20100232078
- Publication date Sep 16, 2010
- Dipankar Bhattacharya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bias circuit scheme for improved reliability in high voltage supply...
- Publication number 20100141334
- Publication date Jun 10, 2010
- Pankaj Kumar
- G05 - CONTROLLING REGULATING
Information Patent Application
Multiple-Mode Compensated Buffer Circuit
- Publication number 20090002017
- Publication date Jan 1, 2009
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Enhanced Output Impedance Compensation
- Publication number 20080297226
- Publication date Dec 4, 2008
- Dipankar Bhattacharya
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Buffer Circuit Having Multiplexed Voltage Level Translation
- Publication number 20080238399
- Publication date Oct 2, 2008
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Circuit for Selectively Bypassing a Capacitive Element
- Publication number 20080074814
- Publication date Mar 27, 2008
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and Apparatus for Improving Reliability of an Integrated Cir...
- Publication number 20080074171
- Publication date Mar 27, 2008
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Circuit having enhanced input signal range
- Publication number 20070229157
- Publication date Oct 4, 2007
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Voltage level translator circuit with wide supply voltage range
- Publication number 20070176635
- Publication date Aug 2, 2007
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Differential buffer circuit with reduced output common mode variation
- Publication number 20070115030
- Publication date May 24, 2007
- Dipankar Bhattacharya
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Floating well circuit having enhanced latch-up performance
- Publication number 20070075748
- Publication date Apr 5, 2007
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Buffer circuit with multiple voltage range
- Publication number 20070046338
- Publication date Mar 1, 2007
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Buffer circuit with enhanced overvoltage protection
- Publication number 20070019348
- Publication date Jan 25, 2007
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Buffer circuit with current limiting
- Publication number 20060220684
- Publication date Oct 5, 2006
- Samuel Khoo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Power pin to power pin electro-static discharge (ESD) clamp
- Publication number 20060203405
- Publication date Sep 14, 2006
- Dipankar Bhattacharya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-bypassing voltage level translator circuit
- Publication number 20060192587
- Publication date Aug 31, 2006
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Comparator circuit having reduced pulse width distortion
- Publication number 20060170461
- Publication date Aug 3, 2006
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RELIABILITY COMPARATOR WITH HYSTERESIS
- Publication number 20060170462
- Publication date Aug 3, 2006
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Bias circuit having reduced power-up delay
- Publication number 20060145749
- Publication date Jul 6, 2006
- Dipankar Bhattacharya
- G05 - CONTROLLING REGULATING
Information Patent Application
Overvoltage tolerant input buffer
- Publication number 20060103427
- Publication date May 18, 2006
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Electrostatic discharge protection in a semiconductor device
- Publication number 20060092589
- Publication date May 4, 2006
- Dipankar Bhattacharya
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Voltage level translator circuit with feedback
- Publication number 20060066381
- Publication date Mar 30, 2006
- Dipankar Bhattacharya
- H03 - BASIC ELECTRONIC CIRCUITRY

John Christopher Kriz

Person

Patents Grantslast 30 patents

Hybrid impedance compensation in a buffer circuit

Voltage level translator circuit

Current-mode logic buffer with enhanced output swing

Mode latching buffer circuit

Impedance compensation in a buffer circuit

Interfacing between differing voltage level requirements in an inte...

Bias voltage generation to protect input/output (IO) circuits durin...

Electrostatic discharge protection circuit

I/O buffer with low voltage semiconductor devices

Bias circuit scheme for improved reliability in high voltage supply...

Floating well circuit operable in a failsafe condition and a tolera...

Memory device control for self-refresh mode

Multiple-mode compensated buffer circuit

Enhanced output impedance compensation

Circuit for selectively bypassing a capacitive element

Power pin to power pin electro-static discharge (ESD) clamp

Method and apparatus for improving reliability of an integrated cir...

Buffer circuit having multiplexed voltage level translation

Electrostatic discharge protection in a semiconductor device

Circuit having enhanced input signal range

Buffer circuit with enhanced overvoltage protection

Voltage level translator circuit with wide supply voltage range

Comparator circuit having reduced pulse width distortion

Buffer circuit with multiple voltage range

Floating well circuit having enhanced latch-up performance

Buffer circuit with current limiting

Differential buffer circuit with reduced output common mode variation

Reference compensation circuit

Programmable reset signal that is independent of supply voltage ram...

Output buffer with selectable slew rate

Patents Applicationslast 30 patents

Current-Mode Logic Buffer with Enhanced Output Swing

Hybrid Impedance Compensation in a Buffer Circuit

Mode Latching Buffer Circuit

INTERFACING BETWEEN DIFFERING VOLTAGE LEVEL REQUIREMENTS IN AN INTE...

Interfacing between differing voltage level requirements in an inte...

BIAS VOLTAGE GENERATION TO PROTECT INPUT/OUTPUT (IO) CIRCUITS DURIN...

MEMORY DEVICE CONTROL FOR SELF-REFRESH MODE

I/O Buffer with Low Voltage Semiconductor Devices

Electrostatic Discharge Protection Circuit

Bias circuit scheme for improved reliability in high voltage supply...

Multiple-Mode Compensated Buffer Circuit

Enhanced Output Impedance Compensation

Buffer Circuit Having Multiplexed Voltage Level Translation

Circuit for Selectively Bypassing a Capacitive Element

Method and Apparatus for Improving Reliability of an Integrated Cir...

Circuit having enhanced input signal range

Voltage level translator circuit with wide supply voltage range

Differential buffer circuit with reduced output common mode variation

Floating well circuit having enhanced latch-up performance

Buffer circuit with multiple voltage range

Buffer circuit with enhanced overvoltage protection

Buffer circuit with current limiting

Power pin to power pin electro-static discharge (ESD) clamp

Self-bypassing voltage level translator circuit

Comparator circuit having reduced pulse width distortion

RELIABILITY COMPARATOR WITH HYSTERESIS

Bias circuit having reduced power-up delay

Overvoltage tolerant input buffer

Electrostatic discharge protection in a semiconductor device

Voltage level translator circuit with feedback