John Edward Barth Jr.

Person

Williston, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Transforming a logical netlist into a hierarchical parasitic netlist
- Patent number 12,014,127
- Issue date Jun 18, 2024
- Synopsys, Inc.
- Jeffrey C. Herbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-fighting level shifters
- Patent number 11,876,516
- Issue date Jan 16, 2024
- Synopsys, Inc.
- Peter Kwang Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory instance reconfiguration using super leaf cells
- Patent number 11,836,433
- Issue date Dec 5, 2023
- Synopsys, Inc.
- John Edward Barth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing transposable access to a synapse array using a recursive...
- Patent number 11,074,496
- Issue date Jul 27, 2021
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory bypass function for a memory
- Patent number 11,017,873
- Issue date May 25, 2021
- Synopsys, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Array organization and architecture to perform range-match operatio...
- Patent number 10,957,391
- Issue date Mar 23, 2021
- International Business Machines Corporation
- John E. Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Interconnect circuits at three-dimensional (3-D) bonding interfaces...
- Patent number 10,740,282
- Issue date Aug 11, 2020
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for integrated level-shifter and memory clock
- Patent number 10,706,916
- Issue date Jul 7, 2020
- Synopsys, Inc.
- Harold Pilo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory bypass function for a memory
- Patent number 10,650,906
- Issue date May 12, 2020
- Synopsys, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Array organization and architecture to perform range-match operatio...
- Patent number 10,431,307
- Issue date Oct 1, 2019
- International Business Machines Corporation
- John E. Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Faulty core recovery mechanisms for a three-dimensional network on...
- Patent number 10,176,063
- Issue date Jan 8, 2019
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing transposable access to a synapse array using a recursive...
- Patent number 9,965,718
- Issue date May 8, 2018
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnect circuits at three dimensional (3-D) bonding interfaces...
- Patent number 9,940,302
- Issue date Apr 10, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Array of processor core circuits with reversible tiers
- Patent number 9,792,251
- Issue date Oct 17, 2017
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dummy gate structure for electrical isolation of a fin DRAM
- Patent number 9,741,722
- Issue date Aug 22, 2017
- International Business Machines Corporation
- John E. Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic random access memory cell with self-aligned strap
- Patent number 9,735,162
- Issue date Aug 15, 2017
- International Business Machines Corporation
- John E. Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sense amplifier and methods thereof for single ended line sensing
- Patent number 9,620,179
- Issue date Apr 11, 2017
- Invecas, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
TCAM field enable logic
- Patent number 9,613,700
- Issue date Apr 4, 2017
- Invecas, Inc.
- Harold Pilo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Array of processor core circuits with reversible tiers
- Patent number 9,588,937
- Issue date Mar 7, 2017
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vertically integrated memory cell
- Patent number 9,570,363
- Issue date Feb 14, 2017
- International Business Machines Corporation
- John E. Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dynamic random access memory cell with self-aligned strap
- Patent number 9,564,443
- Issue date Feb 7, 2017
- International Business Machines Corporation
- John E. Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sense amplifier having a timing circuit for a presearch and a main...
- Patent number 9,564,183
- Issue date Feb 7, 2017
- Invecas, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier for single-ended sensing
- Patent number 9,564,184
- Issue date Feb 7, 2017
- Invecas, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Dummy gate structure for electrical isolation of a fin DRAM
- Patent number 9,564,445
- Issue date Feb 7, 2017
- International Business Machines Corporation
- John E. Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertically integrated memory cell
- Patent number 9,466,614
- Issue date Oct 11, 2016
- International Business Machines Corporation
- John E. Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical fin eDRAM
- Patent number 9,443,857
- Issue date Sep 13, 2016
- GLOBALFOUNDRIES Inc.
- Brent A. Anderson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect circuits at three-dimensional (3-D) bonding interfaces...
- Patent number 9,368,489
- Issue date Jun 14, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Faulty core recovery mechanisms for a three-dimensional network on...
- Patent number 9,363,137
- Issue date Jun 7, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Electronic circuit for fitting a virtual address range to a physica...
- Patent number 9,343,185
- Issue date May 17, 2016
- International Business Machines Corporation
- John E. Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor-on-oxide structure and method of forming
- Patent number 9,299,769
- Issue date Mar 29, 2016
- GLOBALFOUNDRIES Inc.
- John E. Barth
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
TRANSFORMING LOCAL WIRE THRU RESISTANCES INTO GLOBAL DISTRIBUTED RE...
- Publication number 20230260591
- Publication date Aug 17, 2023
- Synopsys, Inc.
- Jeffrey Herbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE LEVEL-SHIFTER DUAL-RAIL MEMORY ARCHITECTURE
- Publication number 20230260555
- Publication date Aug 17, 2023
- Synopsys, Inc.
- Harold PILO
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSFORMING A LOGICAL NETLIST INTO A HIERARCHICAL PARASITIC NETLIST
- Publication number 20230252208
- Publication date Aug 10, 2023
- Synopsys, Inc.
- Jeffrey C. HERBERT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY INSTANCE RECONFIGURATION USING SUPER LEAF CELLS
- Publication number 20230244844
- Publication date Aug 3, 2023
- Synopsys, Inc.
- John Edward BARTH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-FIGHTING LEVEL SHIFTERS
- Publication number 20220158638
- Publication date May 19, 2022
- Synopsys, Inc.
- Peter Kwang LEE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Memory Bypass Function For A Memory
- Publication number 20200234784
- Publication date Jul 23, 2020
- Synopsys, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Bypass Function For A Memory
- Publication number 20200051658
- Publication date Feb 13, 2020
- Invecas, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Application
ARRAY ORGANIZATION AND ARCHITECTURE TO PERFORM RANGE-MATCH OPERATIO...
- Publication number 20190378572
- Publication date Dec 12, 2019
- International Business Machines Corporation
- John E. BARTH
- G11 - INFORMATION STORAGE
Information Patent Application
PROVIDING TRANSPOSABLE ACCESS TO A SYNAPSE ARRAY USING A RECURSIVE...
- Publication number 20180211163
- Publication date Jul 26, 2018
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES...
- Publication number 20180189233
- Publication date Jul 5, 2018
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARRAY OF PROCESSOR CORE CIRCUITS WITH REVERSIBLE TIERS
- Publication number 20170124024
- Publication date May 4, 2017
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERTICALLY INTEGRATED MEMORY CELL
- Publication number 20160365291
- Publication date Dec 15, 2016
- International Business Machines Corporation
- John E. Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FAULTY CORE RECOVERY MECHANISMS FOR A THREE-DIMENSIONAL NETWORK ON...
- Publication number 20160239393
- Publication date Aug 18, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERCONNECT CIRCUITS AT THREE DIMENSIONAL (3-D) BONDING INTERFACES...
- Publication number 20160232128
- Publication date Aug 11, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERTICAL FIN eDRAM
- Publication number 20160163712
- Publication date Jun 9, 2016
- International Business Machines Corporation
- Brent A. Anderson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FAULTY CORE RECOVERY MECHANISMS FOR A THREE-DIMENSIONAL NETWORK ON...
- Publication number 20160154717
- Publication date Jun 2, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sense Amplifier for Single-ended Sensing
- Publication number 20160148689
- Publication date May 26, 2016
- Invecas, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Application
Sense Amplifier
- Publication number 20160148655
- Publication date May 26, 2016
- Invecas, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Application
Sense Amplifier having a Timing Circuit for a Presearch and a Main...
- Publication number 20160148688
- Publication date May 26, 2016
- Invecas, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Application
INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES...
- Publication number 20160148901
- Publication date May 26, 2016
- International Business Machines Corporation
- Rodrigo Alvarez-Icaza Rivera
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ARRAY ORGANIZATION AND ARCHITECTURE TO PERFORM RANGE-MATCH OPERATIO...
- Publication number 20160099054
- Publication date Apr 7, 2016
- International Business Machines Corporation
- John E. BARTH
- G11 - INFORMATION STORAGE
Information Patent Application
DUMMY GATE STRUCTURE FOR ELECTRICAL ISOLATION OF A FIN DRAM
- Publication number 20160027789
- Publication date Jan 28, 2016
- International Business Machines Corporation
- John E. Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY CELL WITH SELF-ALIGNED STRAP
- Publication number 20160027788
- Publication date Jan 28, 2016
- International Business Machines Corporation
- John E. Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROVIDING TRANSPOSABLE ACCESS TO A SYNAPSE ARRAY USING A RECURSIVE...
- Publication number 20150379396
- Publication date Dec 31, 2015
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERTICALLY INTEGRATED MEMORY CELL
- Publication number 20150348977
- Publication date Dec 3, 2015
- International Business Machines Corporation
- John E. Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROVIDING TRANSPOSABLE ACCESS TO A SYNAPSE ARRAY USING A RECURSIVE...
- Publication number 20150286923
- Publication date Oct 8, 2015
- International Business Machines Corporation
- John V. Arthur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY CELL WITH SELF-ALIGNED STRAP
- Publication number 20150206884
- Publication date Jul 23, 2015
- International Business Machines Corporation
- John E. Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUMMY GATE STRUCTURE FOR ELECTRICAL ISOLATION OF A FIN DRAM
- Publication number 20150206885
- Publication date Jul 23, 2015
- International Business Machines Corporation
- John E. Barth
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ARRAY ORGANIZATION AND ARCHITECTURE TO PERFORM RANGE-MATCH OPERATIO...
- Publication number 20150194214
- Publication date Jul 9, 2015
- International Business Machines Corporation
- John E. BARTH
- G11 - INFORMATION STORAGE
Information Patent Application
GATED-FEEDBACK SENSE AMPLIFIER FOR SINGLE-ENDED LOCAL BIT-LINE MEMO...
- Publication number 20150117120
- Publication date Apr 30, 2015
- International Business Machines Corporation
- John E. Barth
- G11 - INFORMATION STORAGE

John Edward Barth Jr.

Person

Patents Grantslast 30 patents

Transforming a logical netlist into a hierarchical parasitic netlist

Non-fighting level shifters

Memory instance reconfiguration using super leaf cells

Providing transposable access to a synapse array using a recursive...

Memory bypass function for a memory

Array organization and architecture to perform range-match operatio...

Interconnect circuits at three-dimensional (3-D) bonding interfaces...

Method and apparatus for integrated level-shifter and memory clock

Memory bypass function for a memory

Array organization and architecture to perform range-match operatio...

Faulty core recovery mechanisms for a three-dimensional network on...

Providing transposable access to a synapse array using a recursive...

Interconnect circuits at three dimensional (3-D) bonding interfaces...

Array of processor core circuits with reversible tiers

Dummy gate structure for electrical isolation of a fin DRAM

Dynamic random access memory cell with self-aligned strap

Sense amplifier and methods thereof for single ended line sensing

TCAM field enable logic

Array of processor core circuits with reversible tiers

Vertically integrated memory cell

Dynamic random access memory cell with self-aligned strap

Sense amplifier having a timing circuit for a presearch and a main...

Sense amplifier for single-ended sensing

Dummy gate structure for electrical isolation of a fin DRAM

Vertically integrated memory cell

Vertical fin eDRAM

Interconnect circuits at three-dimensional (3-D) bonding interfaces...

Faulty core recovery mechanisms for a three-dimensional network on...

Electronic circuit for fitting a virtual address range to a physica...

Semiconductor-on-oxide structure and method of forming

Patents Applicationslast 30 patents

TRANSFORMING LOCAL WIRE THRU RESISTANCES INTO GLOBAL DISTRIBUTED RE...

INTERFACE LEVEL-SHIFTER DUAL-RAIL MEMORY ARCHITECTURE

TRANSFORMING A LOGICAL NETLIST INTO A HIERARCHICAL PARASITIC NETLIST

MEMORY INSTANCE RECONFIGURATION USING SUPER LEAF CELLS

NON-FIGHTING LEVEL SHIFTERS

Memory Bypass Function For A Memory

Memory Bypass Function For A Memory

ARRAY ORGANIZATION AND ARCHITECTURE TO PERFORM RANGE-MATCH OPERATIO...

PROVIDING TRANSPOSABLE ACCESS TO A SYNAPSE ARRAY USING A RECURSIVE...

INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES...

ARRAY OF PROCESSOR CORE CIRCUITS WITH REVERSIBLE TIERS

VERTICALLY INTEGRATED MEMORY CELL

FAULTY CORE RECOVERY MECHANISMS FOR A THREE-DIMENSIONAL NETWORK ON...

INTERCONNECT CIRCUITS AT THREE DIMENSIONAL (3-D) BONDING INTERFACES...

VERTICAL FIN eDRAM

FAULTY CORE RECOVERY MECHANISMS FOR A THREE-DIMENSIONAL NETWORK ON...

Sense Amplifier for Single-ended Sensing

Sense Amplifier

Sense Amplifier having a Timing Circuit for a Presearch and a Main...

INTERCONNECT CIRCUITS AT THREE-DIMENSIONAL (3-D) BONDING INTERFACES...

ARRAY ORGANIZATION AND ARCHITECTURE TO PERFORM RANGE-MATCH OPERATIO...

DUMMY GATE STRUCTURE FOR ELECTRICAL ISOLATION OF A FIN DRAM

DYNAMIC RANDOM ACCESS MEMORY CELL WITH SELF-ALIGNED STRAP

PROVIDING TRANSPOSABLE ACCESS TO A SYNAPSE ARRAY USING A RECURSIVE...

VERTICALLY INTEGRATED MEMORY CELL

PROVIDING TRANSPOSABLE ACCESS TO A SYNAPSE ARRAY USING A RECURSIVE...

DYNAMIC RANDOM ACCESS MEMORY CELL WITH SELF-ALIGNED STRAP

DUMMY GATE STRUCTURE FOR ELECTRICAL ISOLATION OF A FIN DRAM

ARRAY ORGANIZATION AND ARCHITECTURE TO PERFORM RANGE-MATCH OPERATIO...

GATED-FEEDBACK SENSE AMPLIFIER FOR SINGLE-ENDED LOCAL BIT-LINE MEMO...