John Erik Lindholm

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Queue manager for streaming multiprocessor systems
- Patent number 10,983,699
- Issue date Apr 20, 2021
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Queue manager for streaming multiprocessor systems
- Patent number 10,489,056
- Issue date Nov 26, 2019
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Approach for a configurable phase-based priority scheduler
- Patent number 10,346,212
- Issue date Jul 9, 2019
- NVIDIA Corporation
- Jack Hilaire Choquette
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Beam tracing
- Patent number 10,242,485
- Issue date Mar 26, 2019
- NVIDIA Corporation
- Tero Tapani Karras
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable graphics processor for multithreaded execution of prog...
- Patent number 10,217,184
- Issue date Feb 26, 2019
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tree-based thread management
- Patent number 9,921,847
- Issue date Mar 20, 2018
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tree-based thread management
- Patent number 9,830,161
- Issue date Nov 28, 2017
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable graphics processor for multithreaded execution of prog...
- Patent number 9,659,339
- Issue date May 23, 2017
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indirect function call instructions in a synchronous parallel threa...
- Patent number 9,639,365
- Issue date May 2, 2017
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Beam tracing
- Patent number 9,569,559
- Issue date Feb 14, 2017
- NVIDIA Corporation
- Tero Tapani Karras
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Architecture and instructions for accessing multi-dimensional forma...
- Patent number 9,519,947
- Issue date Dec 13, 2016
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for hardware scheduling of conditional barriers a...
- Patent number 9,448,803
- Issue date Sep 20, 2016
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for hardware scheduling of indexed barriers
- Patent number 9,442,755
- Issue date Sep 13, 2016
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dispatching of instructions for execution by heterogeneous processi...
- Patent number 9,304,775
- Issue date Apr 5, 2016
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using condition codes in the presence of non-numeric values
- Patent number 9,195,460
- Issue date Nov 24, 2015
- NVIDIA Corporation
- Robert Steven Glanville
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Credit-based streaming multiprocessor warp scheduling
- Patent number 9,189,242
- Issue date Nov 17, 2015
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processing unit with a texture return buffer and a texture...
- Patent number 9,171,525
- Issue date Oct 27, 2015
- NVIDIA Corporation
- John Erik Lindholm
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Hardware scheduling of ordered critical code sections
- Patent number 9,158,595
- Issue date Oct 13, 2015
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a pixel offset for evaluating a plane equation
- Patent number 9,058,672
- Issue date Jun 16, 2015
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating clip state for a batch of vertices
- Patent number 8,976,195
- Issue date Mar 10, 2015
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Approach for a configurable phase-based priority scheduler
- Patent number 8,949,841
- Issue date Feb 3, 2015
- NVIDIA Corporation
- Jack Hilaire Choquette
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable graphics processor for multithreaded execution of prog...
- Patent number 8,860,737
- Issue date Oct 14, 2014
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-level scheduler for multi-threaded processing
- Patent number 8,732,711
- Issue date May 20, 2014
- NVIDIA Corporation
- William James Dally
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, method and computer program product for bump mapping
- Patent number 8,730,252
- Issue date May 20, 2014
- NVIDIA Corporation
- Henry P. Moreton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread group scheduler for computing on a parallel thread processor
- Patent number 8,732,713
- Issue date May 20, 2014
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel array architecture for a graphics processor
- Patent number 8,730,249
- Issue date May 20, 2014
- NVIDIA Corporation
- John M. Danskin
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Systems and method for managing divergent threads in a SIMD archite...
- Patent number 8,667,256
- Issue date Mar 4, 2014
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for source operand collector caching
- Patent number 8,639,882
- Issue date Jan 28, 2014
- NVIDIA Corporation
- Jack Hilaire Choquette
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register indexed sampler for texture opcodes
- Patent number 8,624,910
- Issue date Jan 7, 2014
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic load balancing of instructions for execution by heterogeneo...
- Patent number 8,578,387
- Issue date Nov 5, 2013
- NVIDIA Corporation
- Peter C. Mills
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...

Patents Applicationslast 30 patents

Information Patent Application
QUEUE MANAGER FOR STREAMING MULTIPROCESSOR SYSTEMS
- Publication number 20200057560
- Publication date Feb 20, 2020
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUEUE MANAGER FOR STREAMING MULTIPROCESSOR SYSTEMS
- Publication number 20190138210
- Publication date May 9, 2019
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BEAM TRACING
- Publication number 20180182158
- Publication date Jun 28, 2018
- NVIDIA Corporation
- Tero Tapani Karras
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROG...
- Publication number 20170256022
- Publication date Sep 7, 2017
- NVIDIA Corporation
- John Erik LINDHOLM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPROACH FOR A CONFIGURABLE PHASE-BASED PRIORITY SCHEDULER
- Publication number 20170192822
- Publication date Jul 6, 2017
- NVIDIA Corporation
- Jack Hilaire CHOQUETTE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROG...
- Publication number 20160300319
- Publication date Oct 13, 2016
- NVIDIA Corporation
- John Erik LINDHOLM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPROACH FOR A CONFIGURABLE PHASE-BASED PRIORITY SCHEDULER
- Publication number 20160224386
- Publication date Aug 4, 2016
- NVIDIA Corporation
- Jack Hilaire CHOQUETTE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BEAM TRACING
- Publication number 20160071310
- Publication date Mar 10, 2016
- NVIDIA Corporation
- Tero Tapani Karras
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TREE-BASED THREAD MANAGEMENT
- Publication number 20150205606
- Publication date Jul 23, 2015
- NVIDIA Corporation
- John Erik LINDHOLM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TREE-BASED THREAD MANAGEMENT
- Publication number 20150205607
- Publication date Jul 23, 2015
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROG...
- Publication number 20140285500
- Publication date Sep 25, 2014
- NVIDIA Corporation
- John Erik LINDHOLM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR HARDWARE SCHEDULING OF INDEXED BARRIERS
- Publication number 20140282566
- Publication date Sep 18, 2014
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR HARDWARE SCHEDULING OF CONDITIONAL BARRIERS A...
- Publication number 20140258693
- Publication date Sep 11, 2014
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSING UNIT WITH A TEXTURE RETURN BUFFER AND A TEXTURE...
- Publication number 20140240337
- Publication date Aug 28, 2014
- NVIDIA Corporation
- John Erik Lindholm
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Application
APPROACH FOR A CONFIGURABLE PHASE-BASED PRIORITY SCHEDULER
- Publication number 20140189698
- Publication date Jul 3, 2014
- NVIDIA Corporation
- Jack Hilaire CHOQUETTE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE SCHEDULING OF ORDERED CRITICAL CODE SECTIONS
- Publication number 20140123150
- Publication date May 1, 2014
- NVIDIA Corporation
- John Erik LINDHOLM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR SOURCE OPERAND COLLECTOR CACHING
- Publication number 20130159628
- Publication date Jun 20, 2013
- Jack Hilaire CHOQUETTE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INDIRECT FUNCTION CALL INSTRUCTIONS IN A SYNCHRONOUS PARALLEL THREA...
- Publication number 20130138926
- Publication date May 30, 2013
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROG...
- Publication number 20120218267
- Publication date Aug 30, 2012
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD GROUP SCHEDULER FOR COMPUTING ON A PARALLEL THREAD PROCESSOR
- Publication number 20120110586
- Publication date May 3, 2012
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Two-Level Scheduler for Multi-Threaded Processing
- Publication number 20120079503
- Publication date Mar 29, 2012
- William James DALLY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION EXECUTION BASED ON OUTSTANDING LOAD OPERATIONS
- Publication number 20120079241
- Publication date Mar 29, 2012
- William James DALLY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL PROCESSOR ARRAY
- Publication number 20120026175
- Publication date Feb 2, 2012
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL ARRAY ARCHITECTURE FOR A GRAPHICS PROCESSOR
- Publication number 20120026171
- Publication date Feb 2, 2012
- NVIDIA Corporation
- John M. Danskin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING A PIXEL OFFSET FOR EVALUATING A PLANE EQUATION
- Publication number 20110081100
- Publication date Apr 7, 2011
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Architecture and Instructions for Accessing Multi-Dimensional Forma...
- Publication number 20110074802
- Publication date Mar 31, 2011
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Unified Collector Structure for Multi-Bank Register File
- Publication number 20110072243
- Publication date Mar 24, 2011
- Xiaogang Qiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Credit-Based Streaming Multiprocessor Warp Scheduling
- Publication number 20110072244
- Publication date Mar 24, 2011
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTER INDEXED SAMPLER FOR TEXTURE OPCODES
- Publication number 20110069076
- Publication date Mar 24, 2011
- John Erik LINDHOLM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACROSS-THREAD OUT-OF-ORDER INSTRUCTION DISPATCH IN A MULTITHREADED...
- Publication number 20100122067
- Publication date May 13, 2010
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING

John Erik Lindholm

Person

Patents Grantslast 30 patents

Queue manager for streaming multiprocessor systems

Queue manager for streaming multiprocessor systems

Approach for a configurable phase-based priority scheduler

Beam tracing

Programmable graphics processor for multithreaded execution of prog...

Tree-based thread management

Tree-based thread management

Programmable graphics processor for multithreaded execution of prog...

Indirect function call instructions in a synchronous parallel threa...

Beam tracing

Architecture and instructions for accessing multi-dimensional forma...

System and method for hardware scheduling of conditional barriers a...

System and method for hardware scheduling of indexed barriers

Dispatching of instructions for execution by heterogeneous processi...

Using condition codes in the presence of non-numeric values

Credit-based streaming multiprocessor warp scheduling

Graphics processing unit with a texture return buffer and a texture...

Hardware scheduling of ordered critical code sections

Using a pixel offset for evaluating a plane equation

Generating clip state for a batch of vertices

Approach for a configurable phase-based priority scheduler

Programmable graphics processor for multithreaded execution of prog...

Two-level scheduler for multi-threaded processing

System, method and computer program product for bump mapping

Thread group scheduler for computing on a parallel thread processor

Parallel array architecture for a graphics processor

Systems and method for managing divergent threads in a SIMD archite...

Methods and apparatus for source operand collector caching

Register indexed sampler for texture opcodes

Dynamic load balancing of instructions for execution by heterogeneo...

Patents Applicationslast 30 patents

QUEUE MANAGER FOR STREAMING MULTIPROCESSOR SYSTEMS

QUEUE MANAGER FOR STREAMING MULTIPROCESSOR SYSTEMS

BEAM TRACING

PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROG...

APPROACH FOR A CONFIGURABLE PHASE-BASED PRIORITY SCHEDULER

PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROG...

APPROACH FOR A CONFIGURABLE PHASE-BASED PRIORITY SCHEDULER

BEAM TRACING

TREE-BASED THREAD MANAGEMENT

TREE-BASED THREAD MANAGEMENT

PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROG...

SYSTEM AND METHOD FOR HARDWARE SCHEDULING OF INDEXED BARRIERS

SYSTEM AND METHOD FOR HARDWARE SCHEDULING OF CONDITIONAL BARRIERS A...

GRAPHICS PROCESSING UNIT WITH A TEXTURE RETURN BUFFER AND A TEXTURE...

APPROACH FOR A CONFIGURABLE PHASE-BASED PRIORITY SCHEDULER

HARDWARE SCHEDULING OF ORDERED CRITICAL CODE SECTIONS

METHODS AND APPARATUS FOR SOURCE OPERAND COLLECTOR CACHING

INDIRECT FUNCTION CALL INSTRUCTIONS IN A SYNCHRONOUS PARALLEL THREA...

PROGRAMMABLE GRAPHICS PROCESSOR FOR MULTITHREADED EXECUTION OF PROG...

THREAD GROUP SCHEDULER FOR COMPUTING ON A PARALLEL THREAD PROCESSOR

Two-Level Scheduler for Multi-Threaded Processing

INSTRUCTION EXECUTION BASED ON OUTSTANDING LOAD OPERATIONS

HIERARCHICAL PROCESSOR ARRAY

PARALLEL ARRAY ARCHITECTURE FOR A GRAPHICS PROCESSOR

USING A PIXEL OFFSET FOR EVALUATING A PLANE EQUATION

Architecture and Instructions for Accessing Multi-Dimensional Forma...

Unified Collector Structure for Multi-Bank Register File

Credit-Based Streaming Multiprocessor Warp Scheduling

REGISTER INDEXED SAMPLER FOR TEXTURE OPCODES

ACROSS-THREAD OUT-OF-ORDER INSTRUCTION DISPATCH IN A MULTITHREADED...