John G. Ferguson

Person

Tualatin, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Verification of photonic integrated circuits
- Patent number 10,929,590
- Issue date Feb 23, 2021
- Mentor Graphics Corporation
- Ruping Cao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification of photonic integrated circuits
- Patent number 10,185,799
- Issue date Jan 22, 2019
- Mentor Graphics Corporation
- Ruping Cao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rule-check waiver
- Patent number 10,089,432
- Issue date Oct 2, 2018
- Mentor Graphics Corporation
- John G. Ferguson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Waiving density violations
- Patent number 8,572,533
- Issue date Oct 29, 2013
- Mentor Graphics Corporation
- John G. Ferguson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Manufacturability
- Patent number 8,555,212
- Issue date Oct 8, 2013
- Mentor Graphics Corporation
- Joseph D Sawicki
- G05 - CONTROLLING REGULATING
Information Patent Grant
Collaborative environment for physical verification of microdevice...
- Patent number 8,516,399
- Issue date Aug 20, 2013
- Mentor Graphics Corporation
- James M. Paris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Manufacturability
- Patent number 8,375,337
- Issue date Feb 12, 2013
- Mentor Graphics Corporation
- Joseph D Sawicki
Information Patent Grant
Secure exchange of information in electronic design automation
- Patent number 8,302,039
- Issue date Oct 30, 2012
- Mentor Graphics Corporation
- John G. Ferguson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Secure exchange of information in electronic design automation
- Patent number 7,698,664
- Issue date Apr 13, 2010
- John G. Ferguson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure exchange of information in electronic design automation
- Patent number 7,353,468
- Issue date Apr 1, 2008
- John G. Ferguson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-line XOR checking of master cells during integrated circuit desi...
- Patent number 7,284,214
- Issue date Oct 16, 2007
- Mentor Graphics Corporation
- Joseph Andrew LeBritton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure exchange of information in electronic design automation
- Patent number 7,222,312
- Issue date May 22, 2007
- John G. Ferguson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SHAPE MATCHING-BASED LAYOUT VERSUS SCHEMATIC FOR PHOTONIC CIRCUITS
- Publication number 20240303402
- Publication date Sep 12, 2024
- Siemens Industry Software Inc.
- John G. Ferguson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERIFICATION OF PHOTONIC INTEGRATED CIRCUITS
- Publication number 20190114384
- Publication date Apr 18, 2019
- Mentor Graphics Corporation
- Ruping Cao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN-RULE-CHECK WAIVER
- Publication number 20180260511
- Publication date Sep 13, 2018
- John G. Ferguson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Verification Of Photonic Integrated Circuits
- Publication number 20160055289
- Publication date Feb 25, 2016
- Mentor Graphics Corporation
- Ruping Cao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Manufacturability
- Publication number 20140040850
- Publication date Feb 6, 2014
- Mentor Graphics Corporation
- Joseph Sawicki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Analog Rule Check Waiver
- Publication number 20130263074
- Publication date Oct 3, 2013
- Mentor Graphics Corporation
- John G. Ferguson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Waiving Density Violations
- Publication number 20130132918
- Publication date May 23, 2013
- John G. Ferguson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN-RULE-CHECK WAIVER
- Publication number 20120167028
- Publication date Jun 28, 2012
- John G. Ferguson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Incremental Layout Analysis
- Publication number 20120047479
- Publication date Feb 23, 2012
- Mentor Graphics Corporation
- James M. Paris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design-Rule-Check Waiver
- Publication number 20110265054
- Publication date Oct 27, 2011
- John G. Ferguson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Collaborative Environment For Physical Verification Of Microdevice...
- Publication number 20110016444
- Publication date Jan 20, 2011
- James M. Paris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design-Rule-Check Waiver
- Publication number 20100257496
- Publication date Oct 7, 2010
- John G. Ferguson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURE EXCHANGE OF INFORMATION IN ELECTRONIC DESIGN AUTOMATION
- Publication number 20100199107
- Publication date Aug 5, 2010
- John G. Ferguson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Manufacturability
- Publication number 20090235209
- Publication date Sep 17, 2009
- Mentor Graphics Corporation
- Joseph D. Sawicki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURE EXCHANGE OF INFORMATION IN ELECTRONIC DESIGN AUTOMATION
- Publication number 20080148348
- Publication date Jun 19, 2008
- John G. Ferguson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURE EXCHANGE OF INFORMATION IN ELECTRONIC DESIGN AUTOMATION
- Publication number 20070266445
- Publication date Nov 15, 2007
- John G. Ferguson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Secure exchange of information in electronic design automation with...
- Publication number 20060259978
- Publication date Nov 16, 2006
- Fedor G. Pikus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
In-line XOR checking of master cells during integrated circuit desi...
- Publication number 20060090146
- Publication date Apr 27, 2006
- Mentor Graphics Corp.
- Joseph Andrew LeBritton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Defect location identification for microdevice manufacturing and test
- Publication number 20060069958
- Publication date Mar 30, 2006
- Joseph D. Sawicki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design for manufacturability
- Publication number 20050234684
- Publication date Oct 20, 2005
- Mentor Graphics Corp.
- Joseph D. Sawicki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Secure exchange of information in electronic design automation
- Publication number 20050071792
- Publication date Mar 31, 2005
- Mentor Graphics Corporation
- John G. Ferguson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Secure exchange of information in electronic design automation
- Publication number 20050071659
- Publication date Mar 31, 2005
- John G. Ferguson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Design for manufacturability
- Publication number 20050015740
- Publication date Jan 20, 2005
- Mentor Graphics Corp.
- Joseph D. Sawicki
- G06 - COMPUTING CALCULATING COUNTING

John G. Ferguson

Person

Patents Grantslast 30 patents

Verification of photonic integrated circuits

Verification of photonic integrated circuits

Rule-check waiver

Waiving density violations

Manufacturability

Collaborative environment for physical verification of microdevice...

Manufacturability

Secure exchange of information in electronic design automation

Secure exchange of information in electronic design automation

Secure exchange of information in electronic design automation

In-line XOR checking of master cells during integrated circuit desi...

Secure exchange of information in electronic design automation

Patents Applicationslast 30 patents

SHAPE MATCHING-BASED LAYOUT VERSUS SCHEMATIC FOR PHOTONIC CIRCUITS

VERIFICATION OF PHOTONIC INTEGRATED CIRCUITS

DESIGN-RULE-CHECK WAIVER

Verification Of Photonic Integrated Circuits

Manufacturability

Analog Rule Check Waiver

Waiving Density Violations

DESIGN-RULE-CHECK WAIVER

Incremental Layout Analysis

Design-Rule-Check Waiver

Collaborative Environment For Physical Verification Of Microdevice...

Design-Rule-Check Waiver

SECURE EXCHANGE OF INFORMATION IN ELECTRONIC DESIGN AUTOMATION

Manufacturability

SECURE EXCHANGE OF INFORMATION IN ELECTRONIC DESIGN AUTOMATION

SECURE EXCHANGE OF INFORMATION IN ELECTRONIC DESIGN AUTOMATION

Secure exchange of information in electronic design automation with...

In-line XOR checking of master cells during integrated circuit desi...

Defect location identification for microdevice manufacturing and test

Design for manufacturability

Secure exchange of information in electronic design automation

Secure exchange of information in electronic design automation

Design for manufacturability