John Hagerman

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Boxford, MA, US

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Patents Grantslast 30 patents

Information Patent Grant
Concurrent formal verification of logic synthesis
- Patent number 10,643,012
- Issue date May 5, 2020
- Synopsys, Inc.
- Lisa R. McIlwain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rule based hierarchy generation in a circuit design verification sy...
- Patent number 6,530,072
- Issue date Mar 4, 2003
- Chrysalis Symbolic Design, Inc.
- John W. Hagerman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computers systems and methods for verifying representations of a ci...
- Patent number 6,219,821
- Issue date Apr 17, 2001
- Chrysalis Symbolic Design, Inc.
- John Hagerman
- G06 - COMPUTING CALCULATING COUNTING