John Henry Westermann JR.

Person

Endicott, NY, US

People

Patents Applicationslast 30 patents

Information Patent Application
HARDWARE SIMULATION ACCELERATOR DESIGN AND METHOD THAT EXPLOITS A P...
- Publication number 20080270748
- Publication date Oct 30, 2008
- International Business Machines Corporation
- Daniel R. CROUSE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION ENCODING IN A HARDWARE SIMULATION ACCELERATOR
- Publication number 20080243462
- Publication date Oct 2, 2008
- International Business Machines Corporation
- Gernot E. Guenther
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Real-Time Data Stream Decompressor
- Publication number 20080127006
- Publication date May 29, 2008
- International Business Machines Corporation
- Gernot E. Guenther
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Concealment of external array accesses in a hardware simulation acc...
- Publication number 20070162270
- Publication date Jul 12, 2007
- International Business Machines Corporation
- Gernot Eberhard Guenther
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hardware accelerator with a single partition for latches and combin...
- Publication number 20060190232
- Publication date Aug 24, 2006
- International Business Machines Corporation
- Gernot E. Guenther
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient array tracing in a logic simulator machine
- Publication number 20020072889
- Publication date Jun 13, 2002
- IBM CORPORATION
- Harrell Hoffman
- G06 - COMPUTING CALCULATING COUNTING

John Henry Westermann JR.

Person

Patents Applicationslast 30 patents

HARDWARE SIMULATION ACCELERATOR DESIGN AND METHOD THAT EXPLOITS A P...

INSTRUCTION ENCODING IN A HARDWARE SIMULATION ACCELERATOR

Real-Time Data Stream Decompressor

Concealment of external array accesses in a hardware simulation acc...

Hardware accelerator with a single partition for latches and combin...

Efficient array tracing in a logic simulator machine