John Iacoponi

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device configured for avoiding electrical shorting
- Patent number 10,050,118
- Issue date Aug 14, 2018
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Copper based nitride liner passivation layers for conductive copper...
- Patent number 9,318,436
- Issue date Apr 19, 2016
- GLOBALFOUNDRIES Inc.
- Xunyuan Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming a dielectric cap layer on a metal gate structure
- Patent number 9,117,877
- Issue date Aug 25, 2015
- GLOBALFOUNDRIES Inc.
- Xiuyu Cai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electroless fill of trench in semiconductor structure
- Patent number 9,087,881
- Issue date Jul 21, 2015
- GLOBALFOUNDRIES Inc.
- Sean X. Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming semiconductor device with self-aligned contact e...
- Patent number 8,946,075
- Issue date Feb 3, 2015
- GLOBALFOUNDRIES Inc.
- Xiuyu Cai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming semiconductor device with self-aligned contact e...
- Patent number 8,940,633
- Issue date Jan 27, 2015
- GLOBALFOUNDRIES Inc.
- Xiuyu Cai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming copper-based nitride liner/passivation layers fo...
- Patent number 8,859,419
- Issue date Oct 14, 2014
- GLOBALFOUNDRIES Inc.
- Xunyuan Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming conductive copper-based structures using a coppe...
- Patent number 8,753,975
- Issue date Jun 17, 2014
- GLOBALFOUNDRIES Inc.
- Xunyuan Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming a dielectric cap layer on a metal gate structure
- Patent number 8,728,908
- Issue date May 20, 2014
- GLOBALFOUNDRIES Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming an integrated circuit with straightened recess...
- Patent number 8,691,696
- Issue date Apr 8, 2014
- GLOBALFOUNDRIES, INC.
- Xiuyu Cai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for depositing a conductive capping layer on metal lines
- Patent number 8,592,312
- Issue date Nov 26, 2013
- GLOBALFOUNDRIES Inc.
- E. Todd Ryan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhancing structural integrity and defining critical dimensions of...
- Patent number 8,105,943
- Issue date Jan 31, 2012
- GLOBALFOUNDRIES Inc.
- Christof Streck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating semiconductor devices minimizing under-oxid...
- Patent number 7,759,205
- Issue date Jul 20, 2010
- Advanced Micro Devices, Inc.
- Kingsuk Maitra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming semiconductor devices by microwave curing of low-...
- Patent number 7,557,035
- Issue date Jul 7, 2009
- Advanced Micro Devices, Inc.
- E. Todd Ryan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for detecting the endpoint of a chemical-mecha...
- Patent number 6,809,032
- Issue date Oct 26, 2004
- Advanced Micro Devices, Inc.
- Frank Mauersberger
- B24 - GRINDING POLISHING
Information Patent Grant
Integrated circuit structure with dielectric islands in metallized...
- Patent number 6,690,580
- Issue date Feb 10, 2004
- AMD, Inc.
- Cindy K. Goldberg
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for forming an under bump metallurgy layer
- Patent number 6,649,533
- Issue date Nov 18, 2003
- Advanced Micro Devices, Inc.
- John A. Iacoponi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for enhancing endpoint detection of a via etch
- Patent number 6,555,396
- Issue date Apr 29, 2003
- Advanced Micro Devices, Inc.
- Ailian Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming openings for conductive interconnects
- Patent number 6,555,479
- Issue date Apr 29, 2003
- Advanced Micro Devices, Inc.
- Frederick N. Hause
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structure for providing depth of polish feedback
- Patent number 6,514,858
- Issue date Feb 4, 2003
- Advanced Micro Devices, Inc.
- Frederick N. Hause
- B24 - GRINDING POLISHING
Information Patent Grant
Variable grain size in conductors for semiconductor vias and trenches
- Patent number 6,489,683
- Issue date Dec 3, 2002
- Advanced Micro Devices, Inc.
- Sergey D. Lopatin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming copper interconnects
- Patent number 6,489,240
- Issue date Dec 3, 2002
- Advanced Micro Devices, Inc.
- John A. Iacoponi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside contact for integrated circuit and method of forming same
- Patent number 6,468,889
- Issue date Oct 22, 2002
- Advanced Micro Devices, Inc.
- John A. Iacoponi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for detecting voltage contrast in a semiconduc...
- Patent number 6,448,099
- Issue date Sep 10, 2002
- Advanced Micro Devices, Inc.
- John A. Iacoponi
- G01 - MEASURING TESTING
Information Patent Grant
Contact each methodology and integration scheme
- Patent number 6,413,846
- Issue date Jul 2, 2002
- Advanced Micro Devices, Inc.
- Paul R. Besser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Alloy barrier layers for semiconductors
- Patent number 6,362,526
- Issue date Mar 26, 2002
- Advanced Micro Devices, Inc.
- Shekhar Pramanick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing method for semiconductor metalization barrier
- Patent number 6,346,472
- Issue date Feb 12, 2002
- Advanced Micro Devices, Inc.
- Sergey D. Lopatin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Barrier materials for metal interconnect in a semiconductor device
- Patent number 6,344,691
- Issue date Feb 5, 2002
- Advanced Micro Devices, Inc.
- John A. Iacoponi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for ramped current density plating of semiconductor vias and...
- Patent number 6,340,633
- Issue date Jan 22, 2002
- Advanced Micro Devices, Inc.
- Sergey D. Lopatin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor metalization barrier and manufacturing method therefor
- Patent number 6,320,263
- Issue date Nov 20, 2001
- Advanced Micro Devices, Inc.
- Sergey D. Lopatin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE CONFIGURED FOR AVOIDING ELECTRICAL SHORTING
- Publication number 20150318345
- Publication date Nov 5, 2015
- GLOBALFOUNDRIES INC.
- Ruilong XIE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FINFET DEVICE COMPRISING A THERMAL OXIDE REGION POSITIONED BETWEEN...
- Publication number 20150311337
- Publication date Oct 29, 2015
- GLOBALFOUNDRIES INC.
- Xiuyu Cai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING COPPER-BASED NITRIDE LINER/PASSIVATION LAYERS FO...
- Publication number 20140361435
- Publication date Dec 11, 2014
- Xunyuan Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTROLESS FILL OF TRENCH IN SEMICONDUCTOR STRUCTURE
- Publication number 20140252616
- Publication date Sep 11, 2014
- Sean X. Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT E...
- Publication number 20140252424
- Publication date Sep 11, 2014
- GLOBALFOUNDRIES INC.
- Xiuyu Cai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT E...
- Publication number 20140252425
- Publication date Sep 11, 2014
- Xiuyu Cai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING COPPER-BASED NITRIDE LINER/PASSIVATION LAYERS FO...
- Publication number 20140217588
- Publication date Aug 7, 2014
- GLOBALFOUNDRIES INC.
- Xunyuan Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FORMING AN INTEGRATED CIRCUIT WITH STRAIGHTENED RECESS...
- Publication number 20130309868
- Publication date Nov 21, 2013
- GLOBALFOUNDRIES INC.
- Xiuyu Cai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of Forming a Dielectric Cap Layer on a Metal Gate Structure
- Publication number 20130181263
- Publication date Jul 18, 2013
- GLOBALFOUNDRIES INC.
- Xiuyu Cai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of Forming a Dielectric Cap Layer on a Metal Gate Structure
- Publication number 20130040450
- Publication date Feb 14, 2013
- GLOBALFOUNDRIES INC.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING SEMICONDUCTOR DEVICES MINIMIZING UNDER-OXID...
- Publication number 20100184265
- Publication date Jul 22, 2010
- Advanced Micro Devices, Inc.
- Kingsuk Maitra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCING STRUCTURAL INTEGRITY AND DEFINING CRITICAL DIMENSIONS OF...
- Publication number 20100025855
- Publication date Feb 4, 2010
- Christof Streck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOS TRANSISTORS FOR THIN SOI INTEGRATION AND METHODS FOR FABRICATIN...
- Publication number 20090045458
- Publication date Feb 19, 2009
- Advanced Micro Devices, Inc.
- John A. IACOPONI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for depositing a conductive capping layer on metal lines
- Publication number 20080305617
- Publication date Dec 11, 2008
- Advanced Micro Devices, Inc.
- E. Todd Ryan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Combined capping layer and ARC for CU interconnects
- Publication number 20020024139
- Publication date Feb 28, 2002
- Simon S. Chan
- H01 - BASIC ELECTRIC ELEMENTS

John Iacoponi

Person

Patents Grantslast 30 patents

Semiconductor device configured for avoiding electrical shorting

Copper based nitride liner passivation layers for conductive copper...

Methods of forming a dielectric cap layer on a metal gate structure

Electroless fill of trench in semiconductor structure

Methods of forming semiconductor device with self-aligned contact e...

Methods of forming semiconductor device with self-aligned contact e...

Methods of forming copper-based nitride liner/passivation layers fo...

Methods of forming conductive copper-based structures using a coppe...

Methods of forming a dielectric cap layer on a metal gate structure

Methods for forming an integrated circuit with straightened recess...

Method for depositing a conductive capping layer on metal lines

Enhancing structural integrity and defining critical dimensions of...

Methods for fabricating semiconductor devices minimizing under-oxid...

Method of forming semiconductor devices by microwave curing of low-...

Method and apparatus for detecting the endpoint of a chemical-mecha...

Integrated circuit structure with dielectric islands in metallized...

Method and apparatus for forming an under bump metallurgy layer

Method and apparatus for enhancing endpoint detection of a via etch

Method for forming openings for conductive interconnects

Test structure for providing depth of polish feedback

Variable grain size in conductors for semiconductor vias and trenches

Method for forming copper interconnects

Backside contact for integrated circuit and method of forming same

Method and apparatus for detecting voltage contrast in a semiconduc...

Contact each methodology and integration scheme

Alloy barrier layers for semiconductors

Manufacturing method for semiconductor metalization barrier

Barrier materials for metal interconnect in a semiconductor device

Method for ramped current density plating of semiconductor vias and...

Semiconductor metalization barrier and manufacturing method therefor

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE CONFIGURED FOR AVOIDING ELECTRICAL SHORTING

FINFET DEVICE COMPRISING A THERMAL OXIDE REGION POSITIONED BETWEEN...

METHODS OF FORMING COPPER-BASED NITRIDE LINER/PASSIVATION LAYERS FO...

ELECTROLESS FILL OF TRENCH IN SEMICONDUCTOR STRUCTURE

METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT E...

METHODS OF FORMING SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CONTACT E...

METHODS OF FORMING COPPER-BASED NITRIDE LINER/PASSIVATION LAYERS FO...

METHODS FOR FORMING AN INTEGRATED CIRCUIT WITH STRAIGHTENED RECESS...

Methods of Forming a Dielectric Cap Layer on a Metal Gate Structure

Methods of Forming a Dielectric Cap Layer on a Metal Gate Structure

METHODS FOR FABRICATING SEMICONDUCTOR DEVICES MINIMIZING UNDER-OXID...

ENHANCING STRUCTURAL INTEGRITY AND DEFINING CRITICAL DIMENSIONS OF...

MOS TRANSISTORS FOR THIN SOI INTEGRATION AND METHODS FOR FABRICATIN...

Method for depositing a conductive capping layer on metal lines

Combined capping layer and ARC for CU interconnects