John K. DeBrosse

Person

Colchester, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Spin-orbit-torque magnetoresistive random-access memory array
- Patent number 12,020,736
- Issue date Jun 25, 2024
- International Business Machines Corporation
- Daniel Worledge
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic boosting techniques for memory
- Patent number 11,037,645
- Issue date Jun 15, 2021
- International Business Machines Corporation
- Kotb Jabeur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic redundancy for memory
- Patent number 10,839,935
- Issue date Nov 17, 2020
- International Business Machines Corporation
- Daniel Worledge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tunable reference system with sense amplifier offset cancellation f...
- Patent number 10,741,232
- Issue date Aug 11, 2020
- International Business Machines Corporation
- Kotb Jabeur
- G11 - INFORMATION STORAGE
Information Patent Grant
Trimming MRAM sense amp with offset cancellation
- Patent number 10,726,897
- Issue date Jul 28, 2020
- International Business Machines Corporation
- Thomas Martin Maffitt
- G11 - INFORMATION STORAGE
Information Patent Grant
Bad bit register for memory
- Patent number 10,437,665
- Issue date Oct 8, 2019
- International Business Machines Corporation
- John K. DeBrosse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bad bit register for memory
- Patent number 10,394,647
- Issue date Aug 27, 2019
- International Business Machines Corporation
- John K. DeBrosse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Magnetic tunnel junction based anti-fuses with cascoded transistors
- Patent number 10,374,152
- Issue date Aug 6, 2019
- International Business Machines Corporation
- Anthony J. Annunziata
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual power rail cascode driver
- Patent number 10,360,958
- Issue date Jul 23, 2019
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
Three terminal spin hall MRAM
- Patent number 10,229,722
- Issue date Mar 12, 2019
- International Business Machines Corporation
- John K. DeBrosse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Secure off-chip MRAM
- Patent number 10,170,178
- Issue date Jan 1, 2019
- International Business Machines Corporation
- John K. DeBrosse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cascode complimentary dual level shifter
- Patent number 10,115,450
- Issue date Oct 30, 2018
- International Business Machines Corporation
- John K. DeBrosse
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adaptive reference scheme for magnetic memory applications
- Patent number 10,102,896
- Issue date Oct 16, 2018
- Headway Technologies, Inc.
- Guenole Jan
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive error correction in a memory system
- Patent number 9,917,601
- Issue date Mar 13, 2018
- International Business Machines Corporation
- John K. DeBrosse
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
STT MRAM source line configuration
- Patent number 9,875,780
- Issue date Jan 23, 2018
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit line clamp voltage generator for STT MRAM sensing
- Patent number 9,852,784
- Issue date Dec 26, 2017
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory interface for metadata shadowing
- Patent number 9,823,858
- Issue date Nov 21, 2017
- International Business Machines Corporation
- John K. Debrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
STT MRAM midpoint reference cell allowing full write
- Patent number 9,799,386
- Issue date Oct 24, 2017
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory interface for metadata shadowing
- Patent number 9,792,052
- Issue date Oct 17, 2017
- International Business Machines Corporation
- John K. Debrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
STT MRAM common source line array bias scheme
- Patent number 9,786,343
- Issue date Oct 10, 2017
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive reference scheme for magnetic memory applications
- Patent number 9,747,965
- Issue date Aug 29, 2017
- Headway Technologies, Inc.
- Guenole Jan
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit line clamp voltage generator for STT MRAM sensing
- Patent number 9,666,258
- Issue date May 30, 2017
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
Mismatch and noise insensitive sense amplifier circuit for STT MRAM
- Patent number 9,613,674
- Issue date Apr 4, 2017
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory interface for metadata shadowing
- Patent number 9,569,109
- Issue date Feb 14, 2017
- International Business Machines Corporation
- John K. Debrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
Magnetic tunnel junction based anti-fuses with cascoded transistors
- Patent number 9,536,926
- Issue date Jan 3, 2017
- International Business Machines Corporation
- Anthony J. Annunziata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nonvolatile memory interface for metadata shadowing
- Patent number 9,496,018
- Issue date Nov 15, 2016
- International Business Machines Corporation
- John K. Debrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive error correction in a memory system
- Patent number 9,495,242
- Issue date Nov 15, 2016
- International Business Machines Corporation
- John K. DeBrosse
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Structure and fabrication of memory array with epitaxially grown me...
- Patent number 9,478,736
- Issue date Oct 25, 2016
- International Business Machines Corporation
- John K. DeBrosse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Adaptive error correction in a memory system
- Patent number 9,471,422
- Issue date Oct 18, 2016
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Grant
Spin torque transfer MRAM device formed on silicon stud grown by se...
- Patent number 9,450,179
- Issue date Sep 20, 2016
- International Business Machines Corporation
- John K. DeBrosse
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SPIN-ORBIT-TORQUE MAGNETORESISTIVE RANDOM-ACCESS MEMORY ARRAY
- Publication number 20230049812
- Publication date Feb 16, 2023
- International Business Machines Corporation
- Daniel Worledge
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC BOOSTING TECHNIQUES FOR MEMORY
- Publication number 20200411128
- Publication date Dec 31, 2020
- International Business Machines Corporation
- Kotb Jabeur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC REDUNDANCY FOR MEMORY
- Publication number 20200250029
- Publication date Aug 6, 2020
- International Business Machines Corporation
- Daniel Worledge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Three Terminal Spin Hall MRAM
- Publication number 20190043547
- Publication date Feb 7, 2019
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Application
BAD BIT REGISTER FOR MEMORY
- Publication number 20180373588
- Publication date Dec 27, 2018
- International Business Machines Corporation
- John K. DeBrosse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BAD BIT REGISTER FOR MEMORY
- Publication number 20180373589
- Publication date Dec 27, 2018
- International Business Machines Corporation
- John K. DeBrosse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL POWER RAIL CASCODE DRIVER
- Publication number 20180358062
- Publication date Dec 13, 2018
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Application
SECURE OFF-CHIP MRAM
- Publication number 20180330779
- Publication date Nov 15, 2018
- International Business Machines Corporation
- John K. DeBrosse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptive Reference Scheme for Magnetic Memory Applications
- Publication number 20170352395
- Publication date Dec 7, 2017
- HEADWAY TECHNOLOGIES, INC.
- Guenole Jan
- G11 - INFORMATION STORAGE
Information Patent Application
Adaptive Reference Scheme for Magnetic Memory Applications
- Publication number 20170186472
- Publication date Jun 29, 2017
- HEADWAY TECHNOLOGIES, INC.
- Guenole Jan
- G11 - INFORMATION STORAGE
Information Patent Application
MAGNETIC TUNNEL JUNCTION BASED ANTI-FUSES WITH CASCODED TRANSISTORS
- Publication number 20170179380
- Publication date Jun 22, 2017
- International Business Machines Corporation
- Anthony J. Annunziata
- G11 - INFORMATION STORAGE
Information Patent Application
Bit Line Clamp Voltage Generator for STT MRAM Sensing
- Publication number 20170125080
- Publication date May 4, 2017
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Application
NONVOLATILE MEMORY INTERFACE FOR METADATA SHADOWING
- Publication number 20170075592
- Publication date Mar 16, 2017
- International Business Machines Corporation
- JOHN K. DEBROSSE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bit Line Clamp Voltage Generator for STT MRAM Sensing
- Publication number 20170047102
- Publication date Feb 16, 2017
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Application
NONVOLATILE MEMORY INTERFACE FOR METADATA SHADOWING
- Publication number 20170017396
- Publication date Jan 19, 2017
- International Business Machines Corporation
- JOHN K. DEBROSSE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE ERROR CORRECTION IN A MEMORY SYSTEM
- Publication number 20160344427
- Publication date Nov 24, 2016
- International Business Machines Corporation
- John K. DeBrosse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NONVOLATILE MEMORY INTERFACE FOR METADATA SHADOWING
- Publication number 20160293241
- Publication date Oct 6, 2016
- International Business Machines Corporation
- JOHN K. DEBROSSE
- G11 - INFORMATION STORAGE
Information Patent Application
NONVOLATILE MEMORY INTERFACE FOR METADATA SHADOWING
- Publication number 20160291870
- Publication date Oct 6, 2016
- International Business Machines Corporation
- JOHN K. DEBROSSE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MISMATCH AND NOISE INSENSITIVE STT MRAM
- Publication number 20160267958
- Publication date Sep 15, 2016
- International Business Machines Corporation
- John K. DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Application
SPIN TORQUE TRANSFER MRAM DEVICE FORMED ON SILICON STUD GROWN BY SE...
- Publication number 20160248003
- Publication date Aug 25, 2016
- International Business Machines Corporation
- John K. DeBrosse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STT-MRAM SENSING TECHNIQUE
- Publication number 20160078914
- Publication date Mar 17, 2016
- International Business Machines Corporation
- John DeBrosse
- G11 - INFORMATION STORAGE
Information Patent Application
ADAPTIVE ERROR CORRECTION IN A MEMORY SYSTEM
- Publication number 20160036466
- Publication date Feb 4, 2016
- International Business Machines Corporation
- John K. DeBrosse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE ERROR CORRECTION IN A MEMORY SYSTEM
- Publication number 20160034350
- Publication date Feb 4, 2016
- International Business Machines Corporation
- John K. DeBrosse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Offset-Cancelling Self-Reference STT-MRAM Sense Amplifier
- Publication number 20150294706
- Publication date Oct 15, 2015
- International Business Machines Corporation
- Anthony R. Bonaccio
- G11 - INFORMATION STORAGE
Information Patent Application
READ CIRCUIT FOR MEMORY
- Publication number 20150138879
- Publication date May 21, 2015
- International Business Machines Corporation
- Jonathan Z. Sun
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY WITH SELF-ALIGNED EPITAXIALLY GROWN MEMORY ELEMENTS AN...
- Publication number 20140273285
- Publication date Sep 18, 2014
- International Business Machines Corporation
- John K. DeBrosse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND FABRICATION OF MEMORY ARRAY WITH EPITAXIALLY GROWN ME...
- Publication number 20140264512
- Publication date Sep 18, 2014
- International Business Machines Corporation
- John K. DeBrosse
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PARALLEL SHUNT PATHS IN THERMALLY ASSISTED MAGNETIC MEMORY CELLS
- Publication number 20140264664
- Publication date Sep 18, 2014
- International Business Machines Corporation
- David W. Abraham
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CELL DESIGN FOR EMBEDDED THERMALLY-ASSISTED MRAM
- Publication number 20140264670
- Publication date Sep 18, 2014
- International Business Machines Corporation
- Anthony J. Annunziata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPIN HALL EFFECT ASSISTED SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCE...
- Publication number 20140264511
- Publication date Sep 18, 2014
- International Business Machines Corporation
- John K. De Brosse
- G11 - INFORMATION STORAGE

John K. DeBrosse

Person

Patents Grantslast 30 patents

Spin-orbit-torque magnetoresistive random-access memory array

Dynamic boosting techniques for memory

Dynamic redundancy for memory

Tunable reference system with sense amplifier offset cancellation f...

Trimming MRAM sense amp with offset cancellation

Bad bit register for memory

Bad bit register for memory

Magnetic tunnel junction based anti-fuses with cascoded transistors

Dual power rail cascode driver

Three terminal spin hall MRAM

Secure off-chip MRAM

Cascode complimentary dual level shifter

Adaptive reference scheme for magnetic memory applications

Adaptive error correction in a memory system

STT MRAM source line configuration

Bit line clamp voltage generator for STT MRAM sensing

Nonvolatile memory interface for metadata shadowing

STT MRAM midpoint reference cell allowing full write

Nonvolatile memory interface for metadata shadowing

STT MRAM common source line array bias scheme

Adaptive reference scheme for magnetic memory applications

Bit line clamp voltage generator for STT MRAM sensing

Mismatch and noise insensitive sense amplifier circuit for STT MRAM

Nonvolatile memory interface for metadata shadowing

Magnetic tunnel junction based anti-fuses with cascoded transistors

Nonvolatile memory interface for metadata shadowing

Adaptive error correction in a memory system

Structure and fabrication of memory array with epitaxially grown me...

Adaptive error correction in a memory system

Spin torque transfer MRAM device formed on silicon stud grown by se...

Patents Applicationslast 30 patents

SPIN-ORBIT-TORQUE MAGNETORESISTIVE RANDOM-ACCESS MEMORY ARRAY

DYNAMIC BOOSTING TECHNIQUES FOR MEMORY

DYNAMIC REDUNDANCY FOR MEMORY

Three Terminal Spin Hall MRAM

BAD BIT REGISTER FOR MEMORY

BAD BIT REGISTER FOR MEMORY

DUAL POWER RAIL CASCODE DRIVER

SECURE OFF-CHIP MRAM

Adaptive Reference Scheme for Magnetic Memory Applications

Adaptive Reference Scheme for Magnetic Memory Applications

MAGNETIC TUNNEL JUNCTION BASED ANTI-FUSES WITH CASCODED TRANSISTORS

Bit Line Clamp Voltage Generator for STT MRAM Sensing

NONVOLATILE MEMORY INTERFACE FOR METADATA SHADOWING

Bit Line Clamp Voltage Generator for STT MRAM Sensing

NONVOLATILE MEMORY INTERFACE FOR METADATA SHADOWING

ADAPTIVE ERROR CORRECTION IN A MEMORY SYSTEM

NONVOLATILE MEMORY INTERFACE FOR METADATA SHADOWING

NONVOLATILE MEMORY INTERFACE FOR METADATA SHADOWING

MISMATCH AND NOISE INSENSITIVE STT MRAM

SPIN TORQUE TRANSFER MRAM DEVICE FORMED ON SILICON STUD GROWN BY SE...

STT-MRAM SENSING TECHNIQUE

ADAPTIVE ERROR CORRECTION IN A MEMORY SYSTEM

ADAPTIVE ERROR CORRECTION IN A MEMORY SYSTEM

Offset-Cancelling Self-Reference STT-MRAM Sense Amplifier

READ CIRCUIT FOR MEMORY

MEMORY ARRAY WITH SELF-ALIGNED EPITAXIALLY GROWN MEMORY ELEMENTS AN...

STRUCTURE AND FABRICATION OF MEMORY ARRAY WITH EPITAXIALLY GROWN ME...

PARALLEL SHUNT PATHS IN THERMALLY ASSISTED MAGNETIC MEMORY CELLS

CELL DESIGN FOR EMBEDDED THERMALLY-ASSISTED MRAM

SPIN HALL EFFECT ASSISTED SPIN TRANSFER TORQUE MAGNETIC RANDOM ACCE...