John L. Hagen

Person

Marion, IA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Product line avionics system multi-core analysis architecture
- Patent number 11,048,548
- Issue date Jun 29, 2021
- Rockwell Collins, Inc.
- Jonathan W. Polley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-core optimized warm-start loading approach
- Patent number 10,445,007
- Issue date Oct 15, 2019
- Rockwell Collins, Inc.
- John L. Hagen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore safe PCIe solution
- Patent number 10,162,787
- Issue date Dec 25, 2018
- Rockwell Collins, Inc.
- Wade D. Paustian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for configurable avionics start sequencing
- Patent number 10,088,843
- Issue date Oct 2, 2018
- Rockwell Collins, Inc.
- David J. Radack
- B64 - AIRCRAFT AVIATION COSMONAUTICS
Information Patent Grant
Multi-core guest operating system loading approach
- Patent number 9,965,315
- Issue date May 8, 2018
- Rockwell Collins, Inc.
- John L. Hagen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-core cache coherency built-in test
- Patent number 9,812,221
- Issue date Nov 7, 2017
- Rockwell Collins, Inc.
- John L. Hagen
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-core RAM error detection and correction (EDAC) test
- Patent number 9,652,315
- Issue date May 16, 2017
- Rockwell Collins, Inc.
- Lloyd F. Aquino
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power warning monitor system and method
- Patent number 9,389,665
- Issue date Jul 12, 2016
- Rockwell Collins, Inc.
- John L. Hagen
- B64 - AIRCRAFT AVIATION COSMONAUTICS

John L. Hagen

Person

Patents Grantslast 30 patents

Product line avionics system multi-core analysis architecture

Multi-core optimized warm-start loading approach

Multicore safe PCIe solution

Systems and methods for configurable avionics start sequencing

Multi-core guest operating system loading approach

Multi-core cache coherency built-in test

Multi-core RAM error detection and correction (EDAC) test

Power warning monitor system and method