John M. Danskin

Person

Providence, RI, US

People

Patents Grantslast 30 patents

Information Patent Grant
Assymetric coherent caching for heterogeneous computing
- Patent number 9,727,463
- Issue date Aug 8, 2017
- NVIDIA Corporation
- John Danskin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing fragment operation processing ac...
- Patent number 9,092,170
- Issue date Jul 28, 2015
- NVIDIA Corporation
- John M. Danskin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of correcting a project schedule
- Patent number 8,775,229
- Issue date Jul 8, 2014
- NVIDIA Corporation
- John M. Danskin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel array architecture for a graphics processor
- Patent number 8,730,249
- Issue date May 20, 2014
- NVIDIA Corporation
- John M. Danskin
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
A-Buffer compression for different compression formats
- Patent number 8,654,135
- Issue date Feb 18, 2014
- NVIDIA Corporation
- John M. Danskin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for structuring an A-buffer to support multi-samp...
- Patent number 8,553,041
- Issue date Oct 8, 2013
- NVIDIA Corporation
- John M. Danskin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing compression across a graphics bu...
- Patent number 8,427,496
- Issue date Apr 23, 2013
- NVIDIA Corporation
- Anthony Michael Tamasi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method and system for improving data coherency in a parallel render...
- Patent number 8,379,033
- Issue date Feb 19, 2013
- NVIDIA Corporation
- Steven E. Molnar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interprocessor direct cache writes
- Patent number 8,327,071
- Issue date Dec 4, 2012
- NVIDIA Corporation
- John M. Danskin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical processor array
- Patent number 8,237,705
- Issue date Aug 7, 2012
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for improving data coherency in a parallel render...
- Patent number 8,139,069
- Issue date Mar 20, 2012
- NVIDIA Corporation
- Steven E. Molnar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for structuring an A-buffer to support multi-samp...
- Patent number 8,130,223
- Issue date Mar 6, 2012
- NVIDIA Corporation
- John M. Danskin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple simultaneous context architecture for rebalancing contexts...
- Patent number 8,095,782
- Issue date Jan 10, 2012
- NVIDIA Corporation
- John M. Danskin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for improving data coherency in a parallel render...
- Patent number 8,085,272
- Issue date Dec 27, 2011
- NVIDIA Corporation
- Steven E. Molnar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical processor array
- Patent number 8,077,174
- Issue date Dec 13, 2011
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for structuring an A-buffer
- Patent number 8,040,349
- Issue date Oct 18, 2011
- NVIDIA Corporation
- John M. Danskin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for structuring an A-buffer
- Patent number 8,026,912
- Issue date Sep 27, 2011
- NVIDIA Corporation
- John M. Danskin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple simultaneous context architecture
- Patent number 7,979,683
- Issue date Jul 12, 2011
- NVIDIA Corporation
- John M. Danskin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Screen compression
- Patent number 7,965,895
- Issue date Jun 21, 2011
- NVIDIA Corporation
- John M. Danskin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Multiple data buffers for processing graphics data
- Patent number 7,907,145
- Issue date Mar 15, 2011
- NVIDIA Corporation
- Rui M. Bastos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Connecting multiple pixel shaders to a frame buffer without a crossbar
- Patent number 7,830,392
- Issue date Nov 9, 2010
- NVIDIA Corporation
- John M. Danskin
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Redundant circuit presents connections on specified I/O ports
- Patent number 7,622,947
- Issue date Nov 24, 2009
- NVIDIA Corporation
- John M. Danskin
- G11 - INFORMATION STORAGE
Information Patent Grant
Real-time display post-processing using programmable hardware
- Patent number 7,586,492
- Issue date Sep 8, 2009
- NVIDIA Corporation
- Duncan A. Riach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stippled lines using direct distance evaluation
- Patent number 7,554,546
- Issue date Jun 30, 2009
- NVIDIA Corporation
- Franklin C. Crow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Screen compression
- Patent number 7,342,590
- Issue date Mar 11, 2008
- NVIDIA Corporation
- John M. Danskin
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Stippled lines using direct distance evaluation
- Patent number 7,221,368
- Issue date May 22, 2007
- NVIDIA Corporation
- Franklin C. Crow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple data buffers for processing graphics data
- Patent number 7,098,922
- Issue date Aug 29, 2006
- NVIDIA Corporation
- Rui M. Bastos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for enhancing depth value processing in a graphic...
- Patent number 6,980,208
- Issue date Dec 27, 2005
- NVIDIA Corporation
- John Montrym
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-mode texture compression algorithm
- Patent number 6,959,110
- Issue date Oct 25, 2005
- NVIDIA Corporation
- John M. Danskin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Occlusion culling method and apparatus for graphics systems
- Patent number 6,894,689
- Issue date May 17, 2005
- NVIDIA Corporation
- Edward C. Greene
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ASSYMETRIC COHERENT CACHING FOR HETEROGENEOUS COMPUTING
- Publication number 20160342513
- Publication date Nov 24, 2016
- NVIDIA Corporation
- John Danskin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR IMPROVING DATA COHERENCY IN A PARALLEL RENDER...
- Publication number 20120147027
- Publication date Jun 14, 2012
- Steven E. MOLNAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL PROCESSOR ARRAY
- Publication number 20120026175
- Publication date Feb 2, 2012
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL ARRAY ARCHITECTURE FOR A GRAPHICS PROCESSOR
- Publication number 20120026171
- Publication date Feb 2, 2012
- NVIDIA Corporation
- John M. Danskin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL PROCESSOR ARRAY
- Publication number 20080143730
- Publication date Jun 19, 2008
- NVIDIA Corporation
- John Erik Lindholm
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delayed frame buffer merging with compression
- Publication number 20070268298
- Publication date Nov 22, 2007
- Jonah M. Alben
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Parallel Array Architecture for a Graphics Processor
- Publication number 20070159488
- Publication date Jul 12, 2007
- NVIDIA Corporation
- John M. Danskin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Real-time display post-processing using programmable hardware
- Publication number 20060132491
- Publication date Jun 22, 2006
- NVIDIA Corporation
- Duncan A. Riach
- G06 - COMPUTING CALCULATING COUNTING

John M. Danskin

Person

Patents Grantslast 30 patents

Assymetric coherent caching for heterogeneous computing

Method and system for implementing fragment operation processing ac...

Method of correcting a project schedule

Parallel array architecture for a graphics processor

A-Buffer compression for different compression formats

System and method for structuring an A-buffer to support multi-samp...

Method and system for implementing compression across a graphics bu...

Method and system for improving data coherency in a parallel render...

Interprocessor direct cache writes

Hierarchical processor array

Method and system for improving data coherency in a parallel render...

System and method for structuring an A-buffer to support multi-samp...

Multiple simultaneous context architecture for rebalancing contexts...

Method and system for improving data coherency in a parallel render...

Hierarchical processor array

System and method for structuring an A-buffer

System and method for structuring an A-buffer

Multiple simultaneous context architecture

Screen compression

Multiple data buffers for processing graphics data

Connecting multiple pixel shaders to a frame buffer without a crossbar

Redundant circuit presents connections on specified I/O ports

Real-time display post-processing using programmable hardware

Stippled lines using direct distance evaluation

Screen compression

Stippled lines using direct distance evaluation

Multiple data buffers for processing graphics data

System and method for enhancing depth value processing in a graphic...

Multi-mode texture compression algorithm

Occlusion culling method and apparatus for graphics systems

Patents Applicationslast 30 patents

ASSYMETRIC COHERENT CACHING FOR HETEROGENEOUS COMPUTING

METHOD AND SYSTEM FOR IMPROVING DATA COHERENCY IN A PARALLEL RENDER...

HIERARCHICAL PROCESSOR ARRAY

PARALLEL ARRAY ARCHITECTURE FOR A GRAPHICS PROCESSOR

HIERARCHICAL PROCESSOR ARRAY

Delayed frame buffer merging with compression

Parallel Array Architecture for a Graphics Processor

Real-time display post-processing using programmable hardware