John P. McCormick

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Multi chip module assembly
- Patent number 7,041,516
- Issue date May 9, 2006
- LSI Logic Corporation
- Sarathy Rajagopalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via construction for structural support
- Patent number 6,943,446
- Issue date Sep 13, 2005
- LSI Logic Corporation
- John P. McCormick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming electrolytic contact pads including layers of cop...
- Patent number 6,777,314
- Issue date Aug 17, 2004
- LSI Logic Corporation
- Kishor Desai
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Bonding pad interface
- Patent number 6,706,622
- Issue date Mar 16, 2004
- LSI Logic Corporation
- John P. McCormick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip-over-chip integrated circuit package
- Patent number 6,558,978
- Issue date May 6, 2003
- LSI Logic Corporation
- John P. McCormick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for attaching solderballs by selectively oxidizing traces
- Patent number 6,431,432
- Issue date Aug 13, 2002
- LSI Logic Corporation
- John Pierre McCormick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertically integrated flip chip semiconductor package
- Patent number 6,369,448
- Issue date Apr 9, 2002
- LSI Logic Corporation
- John P. McCormick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-thickness solder mask in integrated circuit package
- Patent number 6,294,840
- Issue date Sep 25, 2001
- LSI Logic Corporation
- John P. McCormick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer tab tape having distinct signal, power and ground plane...
- Patent number 6,171,888
- Issue date Jan 9, 2001
- LSI Logic Corp.
- Brian Lynch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Die clip assembly for semiconductor package
- Patent number 6,166,434
- Issue date Dec 26, 2000
- LSI Logic Corporation
- Kishor V. Desai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic system including packaged integrated circuits with heat...
- Patent number 6,008,991
- Issue date Dec 28, 1999
- LSI Logic Corporation
- Emily Hawthorne
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated heat spreader/stiffener assembly and method of assembly...
- Patent number 6,002,171
- Issue date Dec 14, 1999
- LSI Logic Corporation
- Kishor V. Desai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated heat spreader/stiffener with apertures for semiconductor...
- Patent number 5,909,057
- Issue date Jun 1, 1999
- LSI Logic Corporation
- John P. McCormick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Support assembly for mounting an integrated circuit package on a su...
- Patent number 5,898,575
- Issue date Apr 27, 1999
- LSI Logic Corporation
- Emily Hawthorne
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer tab tape having distinct signal, power and ground plane...
- Patent number 5,854,085
- Issue date Dec 29, 1998
- LSI Logic Corporation
- Kurt Raymond Raab
- G01 - MEASURING TESTING
Information Patent Grant
Power plane for semiconductor device
- Patent number 5,831,836
- Issue date Nov 3, 1998
- LSI Logic
- Jon Long
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic system using multi-layer tab tape semiconductor device h...
- Patent number 5,801,432
- Issue date Sep 1, 1998
- LSI Logic Corporation
- Michael D. Rostoker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit underfill reservoir
- Patent number 5,780,924
- Issue date Jul 14, 1998
- LSI Logic Corporation
- John P. McCormick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer tape having distinct signal, power and ground planes, s...
- Patent number 5,763,952
- Issue date Jun 9, 1998
- LSI Logic Corporation
- Brian Lynch
- G01 - MEASURING TESTING
Information Patent Grant
Process for manufacturing a multi-layer tab tape semiconductor device
- Patent number 5,681,777
- Issue date Oct 28, 1997
- LSI Logic Corporation
- Brian Lynch
- G01 - MEASURING TESTING
Information Patent Grant
Method of fabricating a wafer probe card for testing an integrated...
- Patent number 5,639,385
- Issue date Jun 17, 1997
- LSI Logic Corporation
- John McCormick
- G01 - MEASURING TESTING
Information Patent Grant
Method of employing multi-layer tab tape in semiconductor device as...
- Patent number 5,638,596
- Issue date Jun 17, 1997
- LSI Logic Corporation
- John McCormick
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor device assembly including power or ground plane which...
- Patent number 5,552,631
- Issue date Sep 3, 1996
- LSI Logic Corporation
- John McCormick
- G01 - MEASURING TESTING
Information Patent Grant
Multi-layer tab tape having distinct signal, power and ground plane...
- Patent number 5,550,406
- Issue date Aug 27, 1996
- LSI Logic Corporation
- John McCormick
- G01 - MEASURING TESTING
Information Patent Grant
Location and standoff pins for chip on tape
- Patent number 5,410,451
- Issue date Apr 25, 1995
- LSI Logic Corporation
- Emily Hawthorne
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Bond pad structure for gold wire bonding to copper low K dielectric...
- Publication number 20060113667
- Publication date Jun 1, 2006
- Chok Chia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Via construction
- Publication number 20040089953
- Publication date May 13, 2004
- John P. McCormick
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Multi chip module assembly
- Publication number 20040072377
- Publication date Apr 15, 2004
- Sarathy Rajagopalan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Electrolytic contact pads
- Publication number 20040023481
- Publication date Feb 5, 2004
- Kishor Desai
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

John P. McCormick

Person

Patents Grantslast 30 patents

Multi chip module assembly

Via construction for structural support

Method of forming electrolytic contact pads including layers of cop...

Bonding pad interface

Chip-over-chip integrated circuit package

Method for attaching solderballs by selectively oxidizing traces

Vertically integrated flip chip semiconductor package

Dual-thickness solder mask in integrated circuit package

Multi-layer tab tape having distinct signal, power and ground plane...

Die clip assembly for semiconductor package

Electronic system including packaged integrated circuits with heat...

Integrated heat spreader/stiffener assembly and method of assembly...

Integrated heat spreader/stiffener with apertures for semiconductor...

Support assembly for mounting an integrated circuit package on a su...

Multi-layer tab tape having distinct signal, power and ground plane...

Power plane for semiconductor device

Electronic system using multi-layer tab tape semiconductor device h...

Integrated circuit underfill reservoir

Multi-layer tape having distinct signal, power and ground planes, s...

Process for manufacturing a multi-layer tab tape semiconductor device

Method of fabricating a wafer probe card for testing an integrated...

Method of employing multi-layer tab tape in semiconductor device as...

Semiconductor device assembly including power or ground plane which...

Multi-layer tab tape having distinct signal, power and ground plane...

Location and standoff pins for chip on tape

Patents Applicationslast 30 patents

Bond pad structure for gold wire bonding to copper low K dielectric...

Via construction

Multi chip module assembly

Electrolytic contact pads