John Pasternak

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San Jose, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Single phase clock-gating circuit
- Patent number 11,159,163
- Issue date Oct 26, 2021
- Synopsys, Inc.
- Pradip Subhana Jadhav
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-bit standard cells for consolidating transistors with selecti...
- Patent number 9,432,003
- Issue date Aug 30, 2016
- Synopsis, Inc.
- John Pasternak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Determination of meta-stable latch bias voltages
- Patent number 8,904,336
- Issue date Dec 2, 2014
- Synopsys, Inc.
- John Henry Pasternak
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SINGLE PHASE CLOCK-GATING CIRCUIT
- Publication number 20200395939
- Publication date Dec 17, 2020
- Synopsys, Inc.
- Pradip Subhana Jadhav
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Multi-Bit Standard Cells For Consolidating Transistors With Selecti...
- Publication number 20150318845
- Publication date Nov 5, 2015
- Synopsys, Inc.
- John Pasternak
- G06 - COMPUTING CALCULATING COUNTING