John R. Goles

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Reference voltage training per path for high speed memory signaling
- Patent number 12,204,751
- Issue date Jan 21, 2025
- Intel Corporation
- Arvind Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input/output (I/O) loopback function for I/O signaling testing
- Patent number 11,662,926
- Issue date May 30, 2023
- Intel Corporation
- Dean-Dexter R. Eugenio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-based dynamic adjustment of memory module bandwidth
- Patent number 10,969,974
- Issue date Apr 6, 2021
- Intel Corporation
- George Vergis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input/output (I/O) loopback function for I/O signaling testing
- Patent number 10,969,979
- Issue date Apr 6, 2021
- Intel Corporation
- Dean-Dexter R. Eugenio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory bus MR register programming process
- Patent number 10,891,243
- Issue date Jan 12, 2021
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to access or operate a dual in-line memory module via mu...
- Patent number 10,592,445
- Issue date Mar 17, 2020
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input/output (I/O) loopback function for I/O signaling testing
- Patent number 10,496,309
- Issue date Dec 3, 2019
- Intel Corporation
- Dean-Dexter R. Eugenio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory bus MR register programming process
- Patent number 10,380,043
- Issue date Aug 13, 2019
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to access or operate a dual in-line memory module via mu...
- Patent number 10,146,711
- Issue date Dec 4, 2018
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHOD FOR PER MEMORY CHIP ADDRESSING
- Publication number 20220276958
- Publication date Sep 1, 2022
- Intel Corporation
- Saravanan SETHURAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE MANAGEABILITY BUS
- Publication number 20210406206
- Publication date Dec 30, 2021
- Intel Corporation
- George Vergis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REFERENCE VOLTAGE TRAINING PER PATH FOR HIGH SPEED MEMORY SIGNALING
- Publication number 20210326041
- Publication date Oct 21, 2021
- Intel Corporation
- Arvind KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REFERENCE VOLTAGE ADJUSTMENT PER PATH FOR HIGH SPEED MEMORY SIGNALING
- Publication number 20210327524
- Publication date Oct 21, 2021
- Intel Corporation
- Arvind KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS, SYSTEM AND METHOD TO DETECT AND IMPROVE AN INPUT CLOCK P...
- Publication number 20210312972
- Publication date Oct 7, 2021
- Arvind A. Kumar
- G11 - INFORMATION STORAGE
Information Patent Application
INPUT/OUTPUT (I/O) LOOPBACK FUNCTION FOR I/O SIGNALING TESTING
- Publication number 20210247919
- Publication date Aug 12, 2021
- Intel Corporation
- Dean-Dexter R. EUGENIO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNIDIRECTIONAL INFORMATION CHANNEL TO MONITOR BIDIRECTIONAL INFORMA...
- Publication number 20200233821
- Publication date Jul 23, 2020
- Intel Corporation
- Arvind KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INPUT/OUTPUT (I/O) LOOPBACK FUNCTION FOR I/O SIGNALING TESTING
- Publication number 20200159429
- Publication date May 21, 2020
- Intel Corporation
- Dean-Dexter R. EUGENIO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY BUS MR REGISTER PROGRAMMING PROCESS
- Publication number 20200065266
- Publication date Feb 27, 2020
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO ACCESS OR OPERATE A DUAL IN-LINE MEMORY MODULE VIA MU...
- Publication number 20190213148
- Publication date Jul 11, 2019
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTENDED MODE (XM) BUS MODE CHANGE, CONFIGURATION REGISTER ACCESSES...
- Publication number 20190188165
- Publication date Jun 20, 2019
- Intel Corporation
- Girish C. Venkatraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY BUS MR REGISTER PROGRAMMING PROCESS
- Publication number 20190095361
- Publication date Mar 28, 2019
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER-BASED DYNAMIC ADJUSTMENT OF MEMORY MODULE BANDWIDTH
- Publication number 20190042121
- Publication date Feb 7, 2019
- George Vergis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INPUT/OUTPUT (I/O) LOOPBACK FUNCTION FOR I/O SIGNALING TESTING
- Publication number 20180136866
- Publication date May 17, 2018
- Intel Corporation
- Dean-Dexter R. EUGENIO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Techniques to Access or Operate a Dual In-Line Memory Module via Mu...
- Publication number 20170199830
- Publication date Jul 13, 2017
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING

John R. Goles

Person

Patents Grantslast 30 patents

Reference voltage training per path for high speed memory signaling

Input/output (I/O) loopback function for I/O signaling testing

Power-based dynamic adjustment of memory module bandwidth

Input/output (I/O) loopback function for I/O signaling testing

Memory bus MR register programming process

Techniques to access or operate a dual in-line memory module via mu...

Input/output (I/O) loopback function for I/O signaling testing

Memory bus MR register programming process

Techniques to access or operate a dual in-line memory module via mu...

Patents Applicationslast 30 patents

APPARATUS AND METHOD FOR PER MEMORY CHIP ADDRESSING

MEMORY DEVICE MANAGEABILITY BUS

REFERENCE VOLTAGE TRAINING PER PATH FOR HIGH SPEED MEMORY SIGNALING

REFERENCE VOLTAGE ADJUSTMENT PER PATH FOR HIGH SPEED MEMORY SIGNALING

APPARATUS, SYSTEM AND METHOD TO DETECT AND IMPROVE AN INPUT CLOCK P...

INPUT/OUTPUT (I/O) LOOPBACK FUNCTION FOR I/O SIGNALING TESTING

UNIDIRECTIONAL INFORMATION CHANNEL TO MONITOR BIDIRECTIONAL INFORMA...

INPUT/OUTPUT (I/O) LOOPBACK FUNCTION FOR I/O SIGNALING TESTING

MEMORY BUS MR REGISTER PROGRAMMING PROCESS

TECHNIQUES TO ACCESS OR OPERATE A DUAL IN-LINE MEMORY MODULE VIA MU...

EXTENDED MODE (XM) BUS MODE CHANGE, CONFIGURATION REGISTER ACCESSES...

MEMORY BUS MR REGISTER PROGRAMMING PROCESS

POWER-BASED DYNAMIC ADJUSTMENT OF MEMORY MODULE BANDWIDTH

INPUT/OUTPUT (I/O) LOOPBACK FUNCTION FOR I/O SIGNALING TESTING

Techniques to Access or Operate a Dual In-Line Memory Module via Mu...