John R. Nickolls

Person

Los Altos, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Instructions for managing a parallel cache hierarchy
- Patent number 10,365,930
- Issue date Jul 30, 2019
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Predicted instruction execution in parallel processors with reduced...
- Patent number 10,360,039
- Issue date Jul 23, 2019
- NVIDIA Corporation
- Richard Craig Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for voting among parallel threads
- Patent number 10,152,328
- Issue date Dec 11, 2018
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache operations and policies for a multi-threaded client
- Patent number 9,952,977
- Issue date Apr 24, 2018
- NVIDIA Corporation
- Steven James Heinrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cooperative thread array reduction and scan operations
- Patent number 9,830,197
- Issue date Nov 28, 2017
- NVIDIA Corporation
- Brian Fahs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indirect function call instructions in a synchronous parallel threa...
- Patent number 9,639,365
- Issue date May 2, 2017
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instructions for managing a parallel cache hierarchy
- Patent number 9,639,479
- Issue date May 2, 2017
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architecture and instructions for accessing multi-dimensional forma...
- Patent number 9,519,947
- Issue date Dec 13, 2016
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cooperative thread array reduction and scan operations
- Patent number 9,417,875
- Issue date Aug 16, 2016
- NVIDIA Corporation
- Brian Fahs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sharing data crossbar for reads and writes in a data cache
- Patent number 9,286,256
- Issue date Mar 15, 2016
- NVIDIA Corporation
- Alexander L. Minkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coalescing memory barrier operations across multiple parallel threads
- Patent number 9,223,578
- Issue date Dec 29, 2015
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient implementation of arrays of structures on SIMT and SIMD a...
- Patent number 8,751,771
- Issue date Jun 10, 2014
- NVIDIA Corporation
- Brian Fahs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thread group scheduler for computing on a parallel thread processor
- Patent number 8,732,713
- Issue date May 20, 2014
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address mapping for a parallel thread processor
- Patent number 8,700,877
- Issue date Apr 15, 2014
- NVIDIA Corporation
- Michael C. Shebanow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unanimous branch instructions in a parallel thread processor
- Patent number 8,677,106
- Issue date Mar 18, 2014
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared single-access memory with management of multiple parallel re...
- Patent number 8,645,638
- Issue date Feb 4, 2014
- NVIDIA Corporation
- Brett W. Coon
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Extended-precision integer arithmetic and logical instructions
- Patent number 8,615,541
- Issue date Dec 24, 2013
- NVIDIA Corporation
- Richard Craig Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unanimous branch instructions in a parallel thread processor
- Patent number 8,615,646
- Issue date Dec 24, 2013
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cooperative thread array reduction and scan operations
- Patent number 8,539,204
- Issue date Sep 17, 2013
- NVIDIA Corporation
- Brian Fahs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Trap handler architecture for a parallel processing unit
- Patent number 8,522,000
- Issue date Aug 27, 2013
- NVIDIA Corporation
- Michael C. Shebanow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for coalescing memory accesses of parallel threads
- Patent number 8,392,669
- Issue date Mar 5, 2013
- NVIDIA Corporation
- Lars Nyland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lock mechanism to enable atomic updates to shared memory
- Patent number 8,375,176
- Issue date Feb 12, 2013
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual architecture and instruction set for parallel thread computing
- Patent number 8,321,849
- Issue date Nov 27, 2012
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Indirect function call instructions in a synchronous parallel threa...
- Patent number 8,312,254
- Issue date Nov 13, 2012
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified addressing and instructions for accessing parallel memory s...
- Patent number 8,271,763
- Issue date Sep 18, 2012
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for voting among parallel threads
- Patent number 8,214,625
- Issue date Jul 3, 2012
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for voting among parallel threads
- Patent number 8,200,947
- Issue date Jun 12, 2012
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared single-access memory with management of multiple parallel re...
- Patent number 8,176,265
- Issue date May 8, 2012
- NVIDIA Corporation
- Brett W. Coon
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Parallel data processing systems and methods using cooperative thre...
- Patent number 8,112,614
- Issue date Feb 7, 2012
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared memory with parallel access and access conflict resolution m...
- Patent number 8,108,625
- Issue date Jan 31, 2012
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INSTRUCTIONS FOR MANAGING A PARALLEL CACHE HIERARCHY
- Publication number 20170235581
- Publication date Aug 17, 2017
- NVIDIA Corporation
- John R. NICKOLLS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS
- Publication number 20160357560
- Publication date Dec 8, 2016
- NVIDIA Corporation
- Brian FAHS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS
- Publication number 20140019724
- Publication date Jan 16, 2014
- NVIDIA Corporation
- Brian FAHS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INDIRECT FUNCTION CALL INSTRUCTIONS IN A SYNCHRONOUS PARALLEL THREA...
- Publication number 20130138926
- Publication date May 30, 2013
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR VOTING AMONG PARALLEL THREADS
- Publication number 20120239909
- Publication date Sep 20, 2012
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED SINGLE-ACCESS MEMORY WITH MANAGEMENT OF MULTIPLE PARALLEL RE...
- Publication number 20120221808
- Publication date Aug 30, 2012
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREAD GROUP SCHEDULER FOR COMPUTING ON A PARALLEL THREAD PROCESSOR
- Publication number 20120110586
- Publication date May 3, 2012
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT IMPLEMENTATION OF ARRAYS OF STRUCTURES ON SIMT AND SIMD A...
- Publication number 20120089792
- Publication date Apr 12, 2012
- Brian FAHS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYTEM FOR PREDICATE-CONTROLLED MULTI-FUNCTION INSTRUCTIONS
- Publication number 20120084539
- Publication date Apr 5, 2012
- Lars S. NYLAND
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOCK MECHANISM TO ENABLE ATOMIC UPDATES TO SHARED MEMORY
- Publication number 20120036329
- Publication date Feb 9, 2012
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED SINGLE ACCESS MEMORY WITH MANAGEMENT OF MULTIPLE PARALLEL RE...
- Publication number 20110252204
- Publication date Oct 13, 2011
- NVIDIA Corporation
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR SCALABLY EXPLOITING PARALLELISM IN A PARALLEL PROCESSIN...
- Publication number 20110238955
- Publication date Sep 29, 2011
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL DATA PROCESSING SYSTEMS AND METHODS USING COOPERATIVE THRE...
- Publication number 20110087860
- Publication date Apr 14, 2011
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Sharing Data Crossbar for Reads and Writes in a Data Cache
- Publication number 20110082961
- Publication date Apr 7, 2011
- Alexander L. Minkin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS
- Publication number 20110078417
- Publication date Mar 31, 2011
- Brian FAHS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Unified Addressing and Instructions for Accessing Parallel Memory S...
- Publication number 20110078406
- Publication date Mar 31, 2011
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Architecture and Instructions for Accessing Multi-Dimensional Forma...
- Publication number 20110074802
- Publication date Mar 31, 2011
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Extended-Precision Integer Arithmetic and Logical Instructions
- Publication number 20110078225
- Publication date Mar 31, 2011
- Richard Craig JOHNSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address Mapping for a Parallel Thread Processor
- Publication number 20110078689
- Publication date Mar 31, 2011
- Michael C. SHEBANOW
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Operations and Policies For A Multi-Threaded Client
- Publication number 20110078381
- Publication date Mar 31, 2011
- Steven James HEINRICH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient Predicated Execution For Parallel Processors
- Publication number 20110078415
- Publication date Mar 31, 2011
- Richard Craig Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COALESCING MEMORY BARRIER OPERATIONS ACROSS MULTIPLE PARALLEL THREADS
- Publication number 20110078692
- Publication date Mar 31, 2011
- John R. NICKOLLS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRAP HANDLER ARCHITECTURE FOR A PARALLEL PROCESSING UNIT
- Publication number 20110078427
- Publication date Mar 31, 2011
- Michael C. Shebanow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNANIMOUS BRANCH INSTRUCTIONS IN A PARALLEL THREAD PROCESSOR
- Publication number 20110072249
- Publication date Mar 24, 2011
- John R. NICKOLLS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNANIMOUS BRANCH INSTRUCTIONS IN A PARALLEL THREAD PROCESSOR
- Publication number 20110072248
- Publication date Mar 24, 2011
- John R. NICKOLLS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS FOR MANAGING A PARALLEL CACHE HIERARCHY
- Publication number 20110072213
- Publication date Mar 24, 2011
- John R. NICKOLLS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Indirect Function Call Instructions in a Synchronous Parallel Threa...
- Publication number 20090240931
- Publication date Sep 24, 2009
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Lock Mechanism to Enable Atomic Updates to Shared Memory
- Publication number 20090240860
- Publication date Sep 24, 2009
- Brett W. Coon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR COALESCING MEMORY ACCESSES OF PARALLEL THREADS
- Publication number 20090240895
- Publication date Sep 24, 2009
- Lars Nyland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL ARCHITECTURE AND INSTRUCTION SET FOR PARALLEL THREAD COMPUTING
- Publication number 20080184211
- Publication date Jul 31, 2008
- NVIDIA Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING

John R. Nickolls

Person

Patents Grantslast 30 patents

Instructions for managing a parallel cache hierarchy

Predicted instruction execution in parallel processors with reduced...

Systems and methods for voting among parallel threads

Cache operations and policies for a multi-threaded client

Cooperative thread array reduction and scan operations

Indirect function call instructions in a synchronous parallel threa...

Instructions for managing a parallel cache hierarchy

Architecture and instructions for accessing multi-dimensional forma...

Cooperative thread array reduction and scan operations

Sharing data crossbar for reads and writes in a data cache

Coalescing memory barrier operations across multiple parallel threads

Efficient implementation of arrays of structures on SIMT and SIMD a...

Thread group scheduler for computing on a parallel thread processor

Address mapping for a parallel thread processor

Unanimous branch instructions in a parallel thread processor

Shared single-access memory with management of multiple parallel re...

Extended-precision integer arithmetic and logical instructions

Unanimous branch instructions in a parallel thread processor

Cooperative thread array reduction and scan operations

Trap handler architecture for a parallel processing unit

Systems and methods for coalescing memory accesses of parallel threads

Lock mechanism to enable atomic updates to shared memory

Virtual architecture and instruction set for parallel thread computing

Indirect function call instructions in a synchronous parallel threa...

Unified addressing and instructions for accessing parallel memory s...

Systems and methods for voting among parallel threads

Systems and methods for voting among parallel threads

Shared single-access memory with management of multiple parallel re...

Parallel data processing systems and methods using cooperative thre...

Shared memory with parallel access and access conflict resolution m...

Patents Applicationslast 30 patents

INSTRUCTIONS FOR MANAGING A PARALLEL CACHE HIERARCHY

COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS

COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS

INDIRECT FUNCTION CALL INSTRUCTIONS IN A SYNCHRONOUS PARALLEL THREA...

SYSTEMS AND METHODS FOR VOTING AMONG PARALLEL THREADS

SHARED SINGLE-ACCESS MEMORY WITH MANAGEMENT OF MULTIPLE PARALLEL RE...

THREAD GROUP SCHEDULER FOR COMPUTING ON A PARALLEL THREAD PROCESSOR

EFFICIENT IMPLEMENTATION OF ARRAYS OF STRUCTURES ON SIMT AND SIMD A...

METHOD AND SYTEM FOR PREDICATE-CONTROLLED MULTI-FUNCTION INSTRUCTIONS

LOCK MECHANISM TO ENABLE ATOMIC UPDATES TO SHARED MEMORY

SHARED SINGLE ACCESS MEMORY WITH MANAGEMENT OF MULTIPLE PARALLEL RE...

METHODS FOR SCALABLY EXPLOITING PARALLELISM IN A PARALLEL PROCESSIN...

PARALLEL DATA PROCESSING SYSTEMS AND METHODS USING COOPERATIVE THRE...

Sharing Data Crossbar for Reads and Writes in a Data Cache

COOPERATIVE THREAD ARRAY REDUCTION AND SCAN OPERATIONS

Unified Addressing and Instructions for Accessing Parallel Memory S...

Architecture and Instructions for Accessing Multi-Dimensional Forma...

Extended-Precision Integer Arithmetic and Logical Instructions

Address Mapping for a Parallel Thread Processor

Cache Operations and Policies For A Multi-Threaded Client

Efficient Predicated Execution For Parallel Processors

COALESCING MEMORY BARRIER OPERATIONS ACROSS MULTIPLE PARALLEL THREADS

TRAP HANDLER ARCHITECTURE FOR A PARALLEL PROCESSING UNIT

UNANIMOUS BRANCH INSTRUCTIONS IN A PARALLEL THREAD PROCESSOR

UNANIMOUS BRANCH INSTRUCTIONS IN A PARALLEL THREAD PROCESSOR

INSTRUCTIONS FOR MANAGING A PARALLEL CACHE HIERARCHY

Indirect Function Call Instructions in a Synchronous Parallel Threa...

Lock Mechanism to Enable Atomic Updates to Shared Memory

SYSTEMS AND METHODS FOR COALESCING MEMORY ACCESSES OF PARALLEL THREADS

VIRTUAL ARCHITECTURE AND INSTRUCTION SET FOR PARALLEL THREAD COMPUTING