John R. Riley

Person

Spicewood, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Negative bitline write assist circuit and method for operating the...
- Patent number 10,902,893
- Issue date Jan 26, 2021
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Grant
Negative bitline write assist circuit and method for operating the...
- Patent number 10,818,326
- Issue date Oct 27, 2020
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Grant
Negative bitline write assist circuit and method for operating the...
- Patent number 9,818,460
- Issue date Nov 14, 2017
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Grant
Sidecar SRAM for high granularity in floor plan aspect ratio
- Patent number 9,575,891
- Issue date Feb 21, 2017
- Advanced Micro Devices, Inc.
- John R. Riley
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell supply voltage reduction prior to write cycle
- Patent number 9,508,414
- Issue date Nov 29, 2016
- Advanced Micro Devices, Inc.
- John R. Riley
- G11 - INFORMATION STORAGE
Information Patent Grant
Negative bitline write assist circuit and method for operating the...
- Patent number 9,378,788
- Issue date Jun 28, 2016
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array test logic
- Patent number 9,355,743
- Issue date May 31, 2016
- Advanced Micro Devices, Inc.
- Amlan Ghosh
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and systems to improve write response times of memory cells
- Patent number 8,068,371
- Issue date Nov 29, 2011
- Intel Corporation
- Feroze A. Merchant
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatuses for operating memory
- Patent number 7,630,228
- Issue date Dec 8, 2009
- Intel Corporation
- John Reginald Riley
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
REGISTER FILE ARRAYS WITH MULTIPLEXED READ PATH CIRCUITRY
- Publication number 20240221825
- Publication date Jul 4, 2024
- John R. Riley
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY UTILIZING BITCELLS WITH SINGLE-ENDED READ CIRCUITRY
- Publication number 20240118826
- Publication date Apr 11, 2024
- Intel Corporation
- Amlan Ghosh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PORTED MEMORY ARRAY UTILIZING BITCELLS WITH BALANCED P-N DIFF...
- Publication number 20240005982
- Publication date Jan 4, 2024
- Amlan Ghosh
- G11 - INFORMATION STORAGE
Information Patent Application
NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE...
- Publication number 20180226109
- Publication date Aug 9, 2018
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Application
NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE...
- Publication number 20180082722
- Publication date Mar 22, 2018
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL VOLTAGE ASYMMETRIC MEMORY CELL
- Publication number 20160379706
- Publication date Dec 29, 2016
- Intel Corporation
- Feroze A. MERCHANT
- G11 - INFORMATION STORAGE
Information Patent Application
NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE...
- Publication number 20160267952
- Publication date Sep 15, 2016
- Intel Corporation
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Application
SIDECAR SRAM FOR HIGH GRANULARITY IN FLOOR PLAN ASPECT RATIO
- Publication number 20150364168
- Publication date Dec 17, 2015
- Advanced Micro Devices, Inc.
- John R. Riley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ARRAY TEST LOGIC
- Publication number 20150318056
- Publication date Nov 5, 2015
- Advanced Micro Devices Inc.
- Amlan Ghosh
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL SUPPLY VOLTAGE REDUCTION PRIOR TO WRITE CYCLE
- Publication number 20140328112
- Publication date Nov 6, 2014
- Advanced Micro Devices, Inc.
- John R. Riley
- G11 - INFORMATION STORAGE
Information Patent Application
NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE...
- Publication number 20140169106
- Publication date Jun 19, 2014
- Pramod Kolar
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND SYSTEMS TO IMPROVE WRITE RESPONSE TIMES OF MEMORY CELLS
- Publication number 20100165756
- Publication date Jul 1, 2010
- I
- Feroze A. Merchant
- G11 - INFORMATION STORAGE

John R. Riley

Person

Patents Grantslast 30 patents

Negative bitline write assist circuit and method for operating the...

Negative bitline write assist circuit and method for operating the...

Negative bitline write assist circuit and method for operating the...

Sidecar SRAM for high granularity in floor plan aspect ratio

Memory cell supply voltage reduction prior to write cycle

Negative bitline write assist circuit and method for operating the...

Memory array test logic

Methods and systems to improve write response times of memory cells

Methods and apparatuses for operating memory

Patents Applicationslast 30 patents

REGISTER FILE ARRAYS WITH MULTIPLEXED READ PATH CIRCUITRY

MEMORY ARRAY UTILIZING BITCELLS WITH SINGLE-ENDED READ CIRCUITRY

MULTI-PORTED MEMORY ARRAY UTILIZING BITCELLS WITH BALANCED P-N DIFF...

NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE...

NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE...

DUAL VOLTAGE ASYMMETRIC MEMORY CELL

NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE...

SIDECAR SRAM FOR HIGH GRANULARITY IN FLOOR PLAN ASPECT RATIO

MEMORY ARRAY TEST LOGIC

MEMORY CELL SUPPLY VOLTAGE REDUCTION PRIOR TO WRITE CYCLE

NEGATIVE BITLINE WRITE ASSIST CIRCUIT AND METHOD FOR OPERATING THE...

METHODS AND SYSTEMS TO IMPROVE WRITE RESPONSE TIMES OF MEMORY CELLS