John Schadt

Person

Bethlehem, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Single event upset immune flip-flop utilizing a small-area highly r...
- Patent number 10,819,318
- Issue date Oct 27, 2020
- Microchip Technology Inc.
- Barry Britton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Serializer with multiple stages
- Patent number 8,912,933
- Issue date Dec 16, 2014
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Simultaneous development of complementary IC families
- Patent number 8,539,409
- Issue date Sep 17, 2013
- Lattice Semiconductor Corporation
- Shawn Murray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-power configurable delay element
- Patent number 8,461,894
- Issue date Jun 11, 2013
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable buffer
- Patent number 8,324,934
- Issue date Dec 4, 2012
- Lattice Semiconductor Corporation
- Keith Truong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Serializer with odd gearing ratio
- Patent number 8,274,412
- Issue date Sep 25, 2012
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low-power, glitch-less, configurable delay element
- Patent number 8,248,136
- Issue date Aug 21, 2012
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Receiver for differential and reference voltage signaling with prog...
- Patent number 7,844,243
- Issue date Nov 30, 2010
- Lattice Semiconductor Corporation
- William B. Andrews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Distributed front-end FIFO for source-synchronous interfaces with n...
- Patent number 7,808,855
- Issue date Oct 5, 2010
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Temperature-independent, linear on-chip termination resistance
- Patent number 7,714,608
- Issue date May 11, 2010
- Lattice Semiconductor Corporation
- Mou C. Lin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Hysteresis-based processing for applications such as signal bias mo...
- Patent number 7,616,029
- Issue date Nov 10, 2009
- Lattice Semiconductor Corporation
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable level shifter
- Patent number 7,605,609
- Issue date Oct 20, 2009
- Lattice Semiconductor Corporation
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit having independent voltage and process/temperatu...
- Patent number 7,586,325
- Issue date Sep 8, 2009
- Lattice Semiconductor Corporation
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Distributed front-end FIFO for source-synchronized interfaces with...
- Patent number 7,573,770
- Issue date Aug 11, 2009
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic over-voltage protection scheme for interface circuitry
- Patent number 7,547,995
- Issue date Jun 16, 2009
- Lattice Semiconductor Corporation
- William B. Andrews
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Receiver for differential and reference-voltage signaling with prog...
- Patent number 7,505,752
- Issue date Mar 17, 2009
- Lattice Semiconductor Corporation
- William B. Andrews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Temperature-independent, linear on-chip termination resistance
- Patent number 7,495,467
- Issue date Feb 24, 2009
- Lattice Semiconductor Corporation
- Mou C. Lin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Output buffer with digital slew control
- Patent number 7,443,192
- Issue date Oct 28, 2008
- Lattice Semiconductor Corporation
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable termination for single-ended and differential schemes
- Patent number 7,262,630
- Issue date Aug 28, 2007
- Lattice Semiconductor Corporation
- William B. Andrews
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Interface circuitry for electrical systems
- Patent number 7,215,149
- Issue date May 8, 2007
- Lattice Semiconductor Corporation
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cascadable memory
- Patent number 7,187,203
- Issue date Mar 6, 2007
- Lattice Semiconductor Corporation
- Christopher Hume
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Synchronous memory
- Patent number 7,183,798
- Issue date Feb 27, 2007
- Lattice Semiconductor Corporation
- Xiaojie He
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic device having a configurable DRAM with transpare...
- Patent number 7,129,749
- Issue date Oct 31, 2006
- Lattice Semiconductor Corporation
- Larry R. Fenstermaker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digitally controlled delay cells
- Patent number 7,009,433
- Issue date Mar 7, 2006
- Lattice Semiconductor Corporation
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic devices with integrated standard-cell logic blocks
- Patent number 6,975,137
- Issue date Dec 13, 2005
- Lattice Semiconductor Corporation
- John A. Schadt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable I/O structure for FPGAs and the like having shared cir...
- Patent number 6,943,582
- Issue date Sep 13, 2005
- Lattice Semiconductor Corporation
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable broadcast initialization of memory blocks
- Patent number 6,940,779
- Issue date Sep 6, 2005
- Lattice Semiconductor Corporation
- Zheng (Jeff) Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit and associated design method with antenna error...
- Patent number 6,877,667
- Issue date Apr 12, 2005
- Lattice Semiconductor Corporation
- Jay H. Angle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic devices with integrated standard-cell logic blocks
- Patent number 6,870,395
- Issue date Mar 22, 2005
- Lattice Semiconductor Corporation
- John A. Schadt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit and associated design method using spare gate is...
- Patent number 6,822,477
- Issue date Nov 23, 2004
- Lattice Semiconductor Corp.
- Craig Bingert
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Temperature-independent, linear on-chip termination resistance
- Publication number 20070164844
- Publication date Jul 19, 2007
- Mou C. Lin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Programmable broadcast initialization of memory blocks
- Publication number 20050035781
- Publication date Feb 17, 2005
- Zheng (Jeff) Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Digitally controlled delay cells
- Publication number 20040239387
- Publication date Dec 2, 2004
- Fulong Zhang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable logic devices with integrated standard-cell logic blocks
- Publication number 20040183564
- Publication date Sep 23, 2004
- Lattice Semiconductor Corporation, a Delaware corporation
- John A. Schadt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Integrated circuit and associated design method with antenna error...
- Publication number 20020167042
- Publication date Nov 14, 2002
- Jay H. Angle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated circuit base transistor structure and associated program...
- Publication number 20020163048
- Publication date Nov 7, 2002
- Stephen R. Cebenko
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit and associated design method using spare gate is...
- Publication number 20020163354
- Publication date Nov 7, 2002
- Craig Bingert
- H01 - BASIC ELECTRIC ELEMENTS

John Schadt

Person

Patents Grantslast 30 patents

Single event upset immune flip-flop utilizing a small-area highly r...

Serializer with multiple stages

Simultaneous development of complementary IC families

Low-power configurable delay element

Programmable buffer

Serializer with odd gearing ratio

Low-power, glitch-less, configurable delay element

Receiver for differential and reference voltage signaling with prog...

Distributed front-end FIFO for source-synchronous interfaces with n...

Temperature-independent, linear on-chip termination resistance

Hysteresis-based processing for applications such as signal bias mo...

Programmable level shifter

Integrated circuit having independent voltage and process/temperatu...

Distributed front-end FIFO for source-synchronized interfaces with...

Dynamic over-voltage protection scheme for interface circuitry

Receiver for differential and reference-voltage signaling with prog...

Temperature-independent, linear on-chip termination resistance

Output buffer with digital slew control

Programmable termination for single-ended and differential schemes

Interface circuitry for electrical systems

Cascadable memory

Synchronous memory

Programmable logic device having a configurable DRAM with transpare...

Digitally controlled delay cells

Programmable logic devices with integrated standard-cell logic blocks

Programmable I/O structure for FPGAs and the like having shared cir...

Programmable broadcast initialization of memory blocks

Integrated circuit and associated design method with antenna error...

Programmable logic devices with integrated standard-cell logic blocks

Integrated circuit and associated design method using spare gate is...

Patents Applicationslast 30 patents

Temperature-independent, linear on-chip termination resistance

Programmable broadcast initialization of memory blocks

Digitally controlled delay cells

Programmable logic devices with integrated standard-cell logic blocks

Integrated circuit and associated design method with antenna error...

Integrated circuit base transistor structure and associated program...

Integrated circuit and associated design method using spare gate is...