John Stephen Muhich

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for controlling a memory array in an information...
- Patent number 6,412,051
- Issue date Jun 25, 2002
- International Business Machines Corp.
- Brian R. Konigsburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for building a multiprocessor data processing system
- Patent number 6,389,585
- Issue date May 14, 2002
- International Business Machines Corporation
- Robert Paul Masleid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for facilitating out-of-order execution of loa...
- Patent number 6,266,767
- Issue date Jul 24, 2001
- International Business Machines Corporation
- Kurt Alan Feiste
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for queuing store data and method therefor
- Patent number 6,167,500
- Issue date Dec 26, 2000
- International Business Machines Corp.
- Kurt Alan Feiste
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for fast unified interrupt recovery and branch...
- Patent number 6,098,167
- Issue date Aug 1, 2000
- International Business Machines Corporation
- Hoichi Cheong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic expansion of execution pipeline stages
- Patent number 6,079,002
- Issue date Jun 20, 2000
- International Business Machines Corporation
- Larry Edward Thatcher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for detecting overlap condition between a stor...
- Patent number 6,070,238
- Issue date May 30, 2000
- International Business Machines Corporation
- Kurt Alan Feiste
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder circuit and method therefor
- Patent number 6,055,557
- Issue date Apr 25, 2000
- International Business Machines Corp.
- John Andrew Beck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forwarding store instruction result to load instruction with reduce...
- Patent number 6,021,485
- Issue date Feb 1, 2000
- International Business Machines Corporation
- Kurt Alan Feiste
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for processing multiple cache misses to a sing...
- Patent number 6,021,467
- Issue date Feb 1, 2000
- International Business Machines Corporation
- Brian R. Konigsburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing system having memory sub-array redundancy and metho...
- Patent number 6,021,512
- Issue date Feb 1, 2000
- International Business Machines Corporation
- George McNeil Lattimore
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for phase rotation in a phase locked loop
- Patent number 6,014,047
- Issue date Jan 11, 2000
- International Business Machines Corporation
- Daniel Mark Dreps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry and method for latching information
- Patent number 6,002,285
- Issue date Dec 14, 1999
- International Business Machines Corporation
- John Stephen Muhich
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for coupled phase locked loops
- Patent number 5,949,262
- Issue date Sep 7, 1999
- International Business Machines Corporation
- Daniel Mark Dreps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Support for out-of-order execution of loads and stores in a processor
- Patent number 5,931,957
- Issue date Aug 3, 1999
- International Business Machines Corporation
- Brian R Konigsburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for instruction fetching using a multi-port in...
- Patent number 5,918,044
- Issue date Jun 29, 1999
- International Business Machines Corporation
- David Stephen Levitan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dispatching instructions in a processor supporting out-of-order exe...
- Patent number 5,913,048
- Issue date Jun 15, 1999
- International Business Machines Corporation
- Hoichi Cheong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Issuing instructions in a processor supporting out-of-order execution
- Patent number 5,887,161
- Issue date Mar 23, 1999
- International Business Machines Corporation
- Hoichi Cheong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for managing register renaming including a wra...
- Patent number 5,872,950
- Issue date Feb 16, 1999
- International Business Machines Corporation
- David Stephen Levitan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for completion of non-interruptible instructio...
- Patent number 5,870,582
- Issue date Feb 9, 1999
- International Business Machines Corporation
- Hoichi Cheong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock generation apparatus and method for CMOS microprocessors usin...
- Patent number 5,870,592
- Issue date Feb 9, 1999
- International Business Machines Corp.
- Daniel Mark Dreps
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for condensed history buffer
- Patent number 5,870,612
- Issue date Feb 9, 1999
- International Business Machines Corporation
- Hoichi Cheong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction dispatch unit and method for dynamically classifying an...
- Patent number 5,864,341
- Issue date Jan 26, 1999
- International Business Machines Corporation
- Troy Neal Hicks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for improved recovery of processor state using...
- Patent number 5,860,014
- Issue date Jan 12, 1999
- International Business Machines Corporation
- Hoichi Cheong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for efficient maintenance of data coherency in a...
- Patent number 5,848,283
- Issue date Dec 8, 1998
- International Business Machines Corporation
- Charles Roberts Moore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for fast parallel determination of queue entries
- Patent number 5,822,752
- Issue date Oct 13, 1998
- International Business Machines Corporation
- Hoichi Cheong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache sub-array method and apparatus for use in microprocessor inte...
- Patent number 5,812,418
- Issue date Sep 22, 1998
- International Business Machines Corporation
- George McNeil Lattimore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for enforcing data coherency in an information...
- Patent number 5,802,571
- Issue date Sep 1, 1998
- International Business Machines Corporation
- Brian R. Konigsburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for performing branch target address calculati...
- Patent number 5,796,998
- Issue date Aug 18, 1998
- International Business Machines Corporation
- David Stephen Levitan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for reduced run-time delay during conditional bra...
- Patent number 5,784,604
- Issue date Jul 21, 1998
- International Business Machines Corporation
- John Stephen Muhich
- G06 - COMPUTING CALCULATING COUNTING

John Stephen Muhich

Person

Patents Grantslast 30 patents

System and method for controlling a memory array in an information...

Method and system for building a multiprocessor data processing system

Apparatus and method for facilitating out-of-order execution of loa...

Mechanism for queuing store data and method therefor

Apparatus and method for fast unified interrupt recovery and branch...

Dynamic expansion of execution pipeline stages

Method and apparatus for detecting overlap condition between a stor...

Adder circuit and method therefor

Forwarding store instruction result to load instruction with reduce...

Apparatus and method for processing multiple cache misses to a sing...

Data processing system having memory sub-array redundancy and metho...

Method and apparatus for phase rotation in a phase locked loop

Circuitry and method for latching information

Method and apparatus for coupled phase locked loops

Support for out-of-order execution of loads and stores in a processor

Apparatus and method for instruction fetching using a multi-port in...

Dispatching instructions in a processor supporting out-of-order exe...

Issuing instructions in a processor supporting out-of-order execution

Method and apparatus for managing register renaming including a wra...

Method and apparatus for completion of non-interruptible instructio...

Clock generation apparatus and method for CMOS microprocessors usin...

Method and apparatus for condensed history buffer

Instruction dispatch unit and method for dynamically classifying an...

Method and apparatus for improved recovery of processor state using...

Method and system for efficient maintenance of data coherency in a...

Method and apparatus for fast parallel determination of queue entries

Cache sub-array method and apparatus for use in microprocessor inte...

Apparatus and method for enforcing data coherency in an information...

Apparatus and method for performing branch target address calculati...

Method and system for reduced run-time delay during conditional bra...