John V. Lovelace

Person

Irmo, SC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory bus MR register programming process
- Patent number 10,891,243
- Issue date Jan 12, 2021
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Measurement and optimization of command signal timing margins
- Patent number 10,621,121
- Issue date Apr 14, 2020
- Intel Corporation
- John V. Lovelace
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast boot up memory controller
- Patent number 10,552,643
- Issue date Feb 4, 2020
- Intel Corporation
- John V. Lovelace
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory bus MR register programming process
- Patent number 10,380,043
- Issue date Aug 13, 2019
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamically adjusting voltage reference to...
- Patent number 10,347,319
- Issue date Jul 9, 2019
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Technologies for reduced control and status register access latency
- Patent number 10,289,431
- Issue date May 14, 2019
- Intel Corporation
- Xueyan Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal phase optimization in memory interface training
- Patent number 10,148,416
- Issue date Dec 4, 2018
- Intel Corporation
- Tonia G Morris
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for encoding registers in a memory module
- Patent number 9,852,021
- Issue date Dec 26, 2017
- Intel Corporation
- Bill Nale
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method for training a control signal based on a strobe signal in a...
- Patent number 9,627,029
- Issue date Apr 18, 2017
- Intel Corporation
- Tonia G. Morris
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for dynamically adjusting voltage reference to...
- Patent number 9,373,365
- Issue date Jun 21, 2016
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for dynamically adjusting voltage reference to...
- Patent number 9,330,734
- Issue date May 3, 2016
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus, method and system to determine memory access command tim...
- Patent number 9,318,182
- Issue date Apr 19, 2016
- Intel Corporation
- John V. Lovelace
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for training a control signal based on a strobe signal in a...
- Patent number 9,025,399
- Issue date May 5, 2015
- Intel Corporation
- Tonia G. Morris
- G11 - INFORMATION STORAGE
Information Patent Grant
Mechanism for detecting a no-processor swap condition and modificat...
- Patent number 8,843,732
- Issue date Sep 23, 2014
- Intel Corporation
- Mahesh S. Natu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Active training of memory command timing
- Patent number 8,819,474
- Issue date Aug 26, 2014
- Intel Corporation
- Theodore Z. Schoenborn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for demand-based memory mirroring
- Patent number 8,601,227
- Issue date Dec 3, 2013
- Intel Corporation
- Robert C. Swanson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dynamically adjusting voltage reference to...
- Patent number 8,582,374
- Issue date Nov 12, 2013
- Intel Corporation
- Christopher Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for evaluating effects of signal phase difference...
- Patent number 8,331,176
- Issue date Dec 11, 2012
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and appratus for demand-based memory mirroring
- Patent number 7,949,850
- Issue date May 24, 2011
- Intel Corporation
- Robert C. Swanson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modular BIOS update mechanism
- Patent number 7,765,409
- Issue date Jul 27, 2010
- Intel Corporation
- Andrew H. Gafken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure method to perform computer system firmware updates
- Patent number 7,305,668
- Issue date Dec 4, 2007
- Intel Corporation
- Barry Kennedy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modular bios update mechanism
- Patent number 7,213,152
- Issue date May 1, 2007
- Intel Corporation
- Andrew H. Gafken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Writing cached data to system management memory
- Patent number 7,107,405
- Issue date Sep 12, 2006
- Intel Corporation
- John V. Lovelace
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Firmware architecture supporting safe updates and multiple processo...
- Patent number 7,036,007
- Issue date Apr 25, 2006
- Intel Corporation
- Todd A. Schelling
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for executing firmware from a valid startup block
- Patent number 6,591,352
- Issue date Jul 8, 2003
- Intel Corporation
- John P. Lambino
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for securing computer firmware wherein unlocki...
- Patent number 6,564,317
- Issue date May 13, 2003
- Intel Corporation
- Robert P. Hale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Operating system bootstrap security mechanism
- Patent number 6,263,431
- Issue date Jul 17, 2001
- Intle Corporation
- John V. Lovelace
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND APPARATUS TO SELECT ADDRESSES FOR MEMORY TRAINING
- Publication number 20240257890
- Publication date Aug 1, 2024
- Intel Corporation
- Zhiguo Wei
- G11 - INFORMATION STORAGE
Information Patent Application
AUTONOMOUS BACKSIDE DATA BUFFER TO MEMORY CHIP WRITE TRAINING CONTROL
- Publication number 20230136268
- Publication date May 4, 2023
- Intel Corporation
- Saravanan SETHURAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTONOMOUS DIMM WRITE LEVELING TRAINING
- Publication number 20230125412
- Publication date Apr 27, 2023
- Intel Corporation
- Saravanan SETHURAMAN
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS TO PERFORM TRAINING ON A DATA BUS BETWEEN A DY...
- Publication number 20230017161
- Publication date Jan 19, 2023
- Intel Corporation
- Saravanan SETHURAMAN
- G11 - INFORMATION STORAGE
Information Patent Application
AUTONOMOUS BACKSIDE CHIP SELECT (CS) AND COMMAND/ADDRESS (CA) TRAIN...
- Publication number 20220300197
- Publication date Sep 22, 2022
- Intel Corporation
- Saravanan SETHURAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MODULE BASED DATA BUFFER COMMUNICATION BUS TRAINING
- Publication number 20220301608
- Publication date Sep 22, 2022
- Intel Corporation
- Saravanan SETHURAMAN
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHOD FOR PER MEMORY CHIP ADDRESSING
- Publication number 20220276958
- Publication date Sep 1, 2022
- Intel Corporation
- Saravanan SETHURAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEFERRED ECC (ERROR CHECKING AND CORRECTION) MEMORY INITIALIZATION...
- Publication number 20210382640
- Publication date Dec 9, 2021
- Intel Corporation
- Sreenivas MANDAVA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY BUS MR REGISTER PROGRAMMING PROCESS
- Publication number 20200065266
- Publication date Feb 27, 2020
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY BUS MR REGISTER PROGRAMMING PROCESS
- Publication number 20190095361
- Publication date Mar 28, 2019
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEASUREMENT AND OPTIMIZATION OF COMMAND SIGNAL TIMING MARGINS
- Publication number 20190034365
- Publication date Jan 31, 2019
- Intel Corporation
- John V. LOVELACE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Module With Integrated Training
- Publication number 20180188959
- Publication date Jul 5, 2018
- Shachi K. Thakkar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR TRAINING ONE OR MORE SIGNAL TIMING RELA...
- Publication number 20180181504
- Publication date Jun 28, 2018
- Intel Corporation
- Tonia Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST BOOT UP MEMORY CONTROLLER
- Publication number 20180181336
- Publication date Jun 28, 2018
- Intel Corporation
- John V. LOVELACE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNOLOGIES FOR REDUCED CONTROL AND STATUS REGISTER ACCESS LATENCY
- Publication number 20180095889
- Publication date Apr 5, 2018
- Intel Corporation
- Xueyan Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNAL PHASE OPTIMIZATION IN MEMORY INTERFACE TRAINING
- Publication number 20180069692
- Publication date Mar 8, 2018
- Intel Corporation
- Tonia G. MORRIS
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTELLIGENT MEMORY SUPPORT FOR PLATFORM RESET OPERATION
- Publication number 20170168747
- Publication date Jun 15, 2017
- Intel Corporation
- Woojong Han
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO...
- Publication number 20160232962
- Publication date Aug 11, 2016
- Intel Corporation
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR ENCODING REGISTERS IN A MEMORY MODULE
- Publication number 20160098366
- Publication date Apr 7, 2016
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR TRAINING A CONTROL SIGNAL BASED ON A STROBE SIGNAL IN A...
- Publication number 20150325281
- Publication date Nov 12, 2015
- Intel Corporation
- Tonia G. MORRIS
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS, METHOD AND SYSTEM TO DETERMINE MEMORY ACCESS COMMAND TIM...
- Publication number 20140211579
- Publication date Jul 31, 2014
- John V. Lovelace
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO...
- Publication number 20140119137
- Publication date May 1, 2014
- Christopher P. MOZAK
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO...
- Publication number 20140063982
- Publication date Mar 6, 2014
- Christopher P. MOZAK
- G11 - INFORMATION STORAGE
Information Patent Application
Methods And Apparatus For Demand-Based Memory Mirroring
- Publication number 20110173385
- Publication date Jul 14, 2011
- Robert C. Swanson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR DETECTING A NO-PROCESSOR SWAP CONDITION AND MODIFICAT...
- Publication number 20110154006
- Publication date Jun 23, 2011
- MAHESH S. NATU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO...
- Publication number 20110141827
- Publication date Jun 16, 2011
- Christopher Mozak
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND SYSTEM FOR EVALUATING EFFECTS OF SIGNAL PHASE DIFFERENCE...
- Publication number 20110131458
- Publication date Jun 2, 2011
- Christopher P. Mozak
- G11 - INFORMATION STORAGE
Information Patent Application
ACTIVE TRAINING OF MEMORY COMMAND TIMING
- Publication number 20100257397
- Publication date Oct 7, 2010
- Theodore Z. Schoenborn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPRATUS FOR DEMAND-BASED MEMORY MIRRORING
- Publication number 20090172323
- Publication date Jul 2, 2009
- Robert C. Swanson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Modular BIOS update mechanism
- Publication number 20070204144
- Publication date Aug 30, 2007
- Andrew H. Gafken
- G06 - COMPUTING CALCULATING COUNTING

John V. Lovelace

Person

Patents Grantslast 30 patents

Memory bus MR register programming process

Measurement and optimization of command signal timing margins

Fast boot up memory controller

Memory bus MR register programming process

Method and apparatus for dynamically adjusting voltage reference to...

Technologies for reduced control and status register access latency

Signal phase optimization in memory interface training

Method and apparatus for encoding registers in a memory module

Method for training a control signal based on a strobe signal in a...

Method and apparatus for dynamically adjusting voltage reference to...

Method and apparatus for dynamically adjusting voltage reference to...

Apparatus, method and system to determine memory access command tim...

Method for training a control signal based on a strobe signal in a...

Mechanism for detecting a no-processor swap condition and modificat...

Active training of memory command timing

Methods and apparatus for demand-based memory mirroring

Method and apparatus for dynamically adjusting voltage reference to...

Method and system for evaluating effects of signal phase difference...

Methods and appratus for demand-based memory mirroring

Modular BIOS update mechanism

Secure method to perform computer system firmware updates

Modular bios update mechanism

Writing cached data to system management memory

Firmware architecture supporting safe updates and multiple processo...

Method and apparatus for executing firmware from a valid startup block

Method and apparatus for securing computer firmware wherein unlocki...

Operating system bootstrap security mechanism

Patents Applicationslast 30 patents

METHODS AND APPARATUS TO SELECT ADDRESSES FOR MEMORY TRAINING

AUTONOMOUS BACKSIDE DATA BUFFER TO MEMORY CHIP WRITE TRAINING CONTROL

AUTONOMOUS DIMM WRITE LEVELING TRAINING

METHOD AND APPARATUS TO PERFORM TRAINING ON A DATA BUS BETWEEN A DY...

AUTONOMOUS BACKSIDE CHIP SELECT (CS) AND COMMAND/ADDRESS (CA) TRAIN...

MEMORY MODULE BASED DATA BUFFER COMMUNICATION BUS TRAINING

APPARATUS AND METHOD FOR PER MEMORY CHIP ADDRESSING

DEFERRED ECC (ERROR CHECKING AND CORRECTION) MEMORY INITIALIZATION...

MEMORY BUS MR REGISTER PROGRAMMING PROCESS

MEMORY BUS MR REGISTER PROGRAMMING PROCESS

MEASUREMENT AND OPTIMIZATION OF COMMAND SIGNAL TIMING MARGINS

Memory Module With Integrated Training

APPARATUSES AND METHODS FOR TRAINING ONE OR MORE SIGNAL TIMING RELA...

FAST BOOT UP MEMORY CONTROLLER

TECHNOLOGIES FOR REDUCED CONTROL AND STATUS REGISTER ACCESS LATENCY

SIGNAL PHASE OPTIMIZATION IN MEMORY INTERFACE TRAINING

INTELLIGENT MEMORY SUPPORT FOR PLATFORM RESET OPERATION

METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO...

METHOD AND APPARATUS FOR ENCODING REGISTERS IN A MEMORY MODULE

METHOD FOR TRAINING A CONTROL SIGNAL BASED ON A STROBE SIGNAL IN A...

APPARATUS, METHOD AND SYSTEM TO DETERMINE MEMORY ACCESS COMMAND TIM...

METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO...

METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO...

Methods And Apparatus For Demand-Based Memory Mirroring

MECHANISM FOR DETECTING A NO-PROCESSOR SWAP CONDITION AND MODIFICAT...

METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO...

METHOD AND SYSTEM FOR EVALUATING EFFECTS OF SIGNAL PHASE DIFFERENCE...

ACTIVE TRAINING OF MEMORY COMMAND TIMING

METHODS AND APPRATUS FOR DEMAND-BASED MEMORY MIRRORING

Modular BIOS update mechanism