John Wai Cheong Fu

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Combined tag and data ECC for enhanced soft error recovery from cac...
- Patent number 7,376,877
- Issue date May 20, 2008
- Intel Corporation
- Nhon Toai Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of correcting a machine check error
- Patent number 6,948,094
- Issue date Sep 20, 2005
- Intel Corporation
- Len Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined tag and data ECC for enhanced soft error recovery from cac...
- Patent number 6,772,383
- Issue date Aug 3, 2004
- Intel Corporation
- Nhon Toai Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing ordered data requests to a memory
- Patent number 6,725,339
- Issue date Apr 20, 2004
- Intel Corporation
- John Wai Cheong Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for managing temporal and non-temporal data in...
- Patent number 6,542,966
- Issue date Apr 1, 2003
- Intel Corporation
- John Crawford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for handling data errors in a computer system
- Patent number 6,453,427
- Issue date Sep 17, 2002
- Intel Corporation
- Nhon T. Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance fully dual-ported, pipelined cache design
- Patent number 6,427,191
- Issue date Jul 30, 2002
- Intel Corporation
- John Wai Cheong Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing ordered data requests to a memory
- Patent number 6,381,678
- Issue date Apr 30, 2002
- Intel Corporation
- John Wai Cheong Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for detecting and compensating for certain sno...
- Patent number 6,292,906
- Issue date Sep 18, 2001
- Intel Corporation
- John W. C. Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-ported, pipelined, two level cache system
- Patent number 6,272,597
- Issue date Aug 7, 2001
- Intel Corporation
- John Wai Cheong Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing cache accesses
- Patent number 6,226,763
- Issue date May 1, 2001
- Intel Corporation
- John Wai Cheong Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for storing data in a memory array
- Patent number 6,134,636
- Issue date Oct 17, 2000
- Intel Corporation
- Gregory Scott Mathews
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for detecting soft errors in content addressab...
- Patent number 6,067,656
- Issue date May 23, 2000
- Intel Corporation
- Stefan Rusu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Combined tag and data ECC for enhanced soft error recovery from cac...
- Publication number 20040199851
- Publication date Oct 7, 2004
- Nhon Toai Quach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of correcting a machine check error
- Publication number 20030074601
- Publication date Apr 17, 2003
- Len Schultz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Processing ordered data requests to a memory
- Publication number 20020073284
- Publication date Jun 13, 2002
- John Wai Cheong Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR HANDLING DATA ERRORS IN A COMPUTER SYSTEM
- Publication number 20010049798
- Publication date Dec 6, 2001
- NHON T. QUACH
- G06 - COMPUTING CALCULATING COUNTING

John Wai Cheong Fu

Person

Patents Grantslast 30 patents

Combined tag and data ECC for enhanced soft error recovery from cac...

Method of correcting a machine check error

Combined tag and data ECC for enhanced soft error recovery from cac...

Processing ordered data requests to a memory

Method and apparatus for managing temporal and non-temporal data in...

Method and apparatus for handling data errors in a computer system

High performance fully dual-ported, pipelined cache design

Processing ordered data requests to a memory

Method and apparatus for detecting and compensating for certain sno...

Dual-ported, pipelined, two level cache system

Method and apparatus for performing cache accesses

Method and apparatus for storing data in a memory array

Method and apparatus for detecting soft errors in content addressab...

Patents Applicationslast 30 patents

Combined tag and data ECC for enhanced soft error recovery from cac...

Method of correcting a machine check error

Processing ordered data requests to a memory

METHOD AND APPARATUS FOR HANDLING DATA ERRORS IN A COMPUTER SYSTEM