John Zapisek

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Scalable processor to processor and processor to I/O interconnectio...
- Patent number 5,598,408
- Issue date Jan 28, 1997
- MasPar Computer Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Broadcasting headers to configure physical devices interfacing a da...
- Patent number 5,488,694
- Issue date Jan 30, 1996
- MasPar Computer Company
- Mark P. McKee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Diagnostic circuitry
- Patent number 5,450,330
- Issue date Sep 12, 1995
- MasPar Computer Corporation
- John Zapisek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Router chip for processing routing address bits and protocol bits u...
- Patent number 5,434,977
- Issue date Jul 18, 1995
- MarPar Computer Corporation
- John Zapisek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Router chip with quad-crossbar and hyperbar personalities
- Patent number 5,345,556
- Issue date Sep 6, 1994
- MasPar Computer Corporation
- John Zapisek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable processor to processor and processor-to-I/O interconnectio...
- Patent number 5,280,474
- Issue date Jan 18, 1994
- MasPar Computer Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Input/output system for parallel processing arrays
- Patent number 5,243,699
- Issue date Sep 7, 1993
- MasPar Computer Corporation
- John R. Nickolls
- G06 - COMPUTING CALCULATING COUNTING

John Zapisek

Person

Patents Grantslast 30 patents

Scalable processor to processor and processor to I/O interconnectio...

Broadcasting headers to configure physical devices interfacing a da...

Diagnostic circuitry

Router chip for processing routing address bits and protocol bits u...

Router chip with quad-crossbar and hyperbar personalities

Scalable processor to processor and processor-to-I/O interconnectio...

Input/output system for parallel processing arrays