Jon Long

Person

Livermore, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit package with electro-optical interconnect circuitry
- Patent number 12,055,777
- Issue date Aug 6, 2024
- Intel Corporation
- Peng Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with electro-optical interconnect circuitry
- Patent number 11,327,259
- Issue date May 10, 2022
- Intel Corporation
- Peng Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device with field programmable optical array
- Patent number 10,212,498
- Issue date Feb 19, 2019
- Altera Corporation
- Mike Peng Li
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Techniques for variable forward error correction
- Patent number 10,075,189
- Issue date Sep 11, 2018
- Altera Corporation
- Peng Li
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Integrated circuit device with field programmable optical array
- Patent number 9,608,728
- Issue date Mar 28, 2017
- Altera Corporation
- Mike Peng Li
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
IC package for pin counts less than test requirements
- Patent number 9,110,128
- Issue date Aug 18, 2015
- Altera Corporation
- Jon M. Long
- G01 - MEASURING TESTING
Information Patent Grant
Electronic assembly apparatus and associated methods
- Patent number 9,040,348
- Issue date May 26, 2015
- Altera Corporation
- Nagesh Vodrahalli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated optical-electronic interface in programmable integrated...
- Patent number 9,002,155
- Issue date Apr 7, 2015
- Altera Corporation
- Peng Li
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for stacking a memory chip above an integrated...
- Patent number 8,716,876
- Issue date May 6, 2014
- Altera Corporation
- Richard G. Smolen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced inductance IC leaded package
- Patent number 8,076,761
- Issue date Dec 13, 2011
- Altera Corporation
- Jon M. Long
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ball grid array package-to-board interconnect co-design apparatus
- Patent number 7,514,789
- Issue date Apr 7, 2009
- Altera Corporation
- Yuming Tao
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Ball grid array package-to-board interconnect co-design apparatus
- Patent number 7,405,477
- Issue date Jul 29, 2008
- Altera Corporation
- Yuming Tao
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Elongated bonding pad for wire bonding and sort probing
- Patent number 7,091,613
- Issue date Aug 15, 2006
- Altera Corporation
- Jon M. Long
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Post-passivation thick metal pre-routing for flip chip packaging
- Patent number 6,864,565
- Issue date Mar 8, 2005
- Altera Corporation
- Vincent Hool
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with universal substrate for electrically int...
- Patent number 6,407,450
- Issue date Jun 18, 2002
- Altera Corporation
- Tarun Verma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power plane for semiconductor device
- Patent number 5,831,836
- Issue date Nov 3, 1998
- LSI Logic
- Jon Long
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming electronic device
- Patent number 5,408,741
- Issue date Apr 25, 1995
- VLSI Technology, Inc.
- Jon M. Long
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-destructive test for inner lead bond of a tab device
- Patent number 5,407,275
- Issue date Apr 18, 1995
- VLSI Technology, Inc.
- Jon M. Long
- G01 - MEASURING TESTING
Information Patent Grant
System for securing and electrically connecting a semiconductor chi...
- Patent number 5,349,495
- Issue date Sep 20, 1994
- VLSI Technology, Inc.
- Thomas A. Visel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of providing a capacitor within a semiconductor device package
- Patent number 5,307,559
- Issue date May 3, 1994
- LSI Logic Corporation
- Jon Long
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System for protecting leads of a semiconductor chip package during...
- Patent number 5,304,738
- Issue date Apr 19, 1994
- VLSI Technology, Inc.
- Jon M. Long
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for bonding a lead to a die pad using an electroless plating...
- Patent number 5,260,234
- Issue date Nov 9, 1993
- VLSI Technology, Inc.
- Jon M. Long
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit die-to-leadframe interconnect assembly system
- Patent number 5,233,131
- Issue date Aug 3, 1993
- VLSI Technology, Inc.
- Louis H. Liang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System for protecting leads to a semiconductor chip package during...
- Patent number 5,221,812
- Issue date Jun 22, 1993
- VLSI Technology, Inc.
- Jon M. Long
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device package having a thermal dissipation means tha...
- Patent number 5,218,215
- Issue date Jun 8, 1993
- VLSI Technology, Inc.
- Louis Liang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electronic device package--carrier assembly ready to be mounted ont...
- Patent number 5,210,375
- Issue date May 11, 1993
- VLSI Technology, Inc.
- Jon M. Long
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor chip cooling apparatus
- Patent number 5,210,440
- Issue date May 11, 1993
- VLSI Technology, Inc.
- Jon M. Long
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with device and wire coat assembly
- Patent number 5,206,794
- Issue date Apr 27, 1993
- VLSI Technology, Inc.
- Jon M. Long
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Internal capacitor arrangement for semiconductor device assembly
- Patent number 5,200,642
- Issue date Apr 6, 1993
- LSI Logic Corporation
- Jon Long
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Heat sink for semiconductor device assembly
- Patent number 5,175,612
- Issue date Dec 29, 1992
- LSI Logic Corporation
- Jon Long
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH ELECTRO-OPTICAL INTERCONNECT CIRCUITRY
- Publication number 20220244477
- Publication date Aug 4, 2022
- Intel Corporation
- Peng Li
- G02 - OPTICS
Information Patent Application
INTEGRATED CIRCUIT PACKAGE WITH ELECTRO-OPTICAL INTERCONNECT CIRCUITRY
- Publication number 20190041594
- Publication date Feb 7, 2019
- Intel Corporation
- Peng Li
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Techniques For Variable Forward Error Correction
- Publication number 20160373138
- Publication date Dec 22, 2016
- Altera Corporation
- Peng Li
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
APPARATUS FOR STACKED ELECTRONIC CIRCUITRY AND ASSOCIATED METHODS
- Publication number 20130069247
- Publication date Mar 21, 2013
- Arifur Rahman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC ASSEMBLY APPARATUS AND ASSOCIATED METHODS
- Publication number 20130071969
- Publication date Mar 21, 2013
- Nagesh Vodrahalli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED OPTICAL-ELECTRONIC INTERFACE IN PROGRAMMABLE INTEGRATED...
- Publication number 20120251116
- Publication date Oct 4, 2012
- Altera Corporation
- Peng Li
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and structure for integrated circuit package
- Publication number 20020145207
- Publication date Oct 10, 2002
- Sidney Larry Anderson
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Integrated circuit package with electro-optical interconnect circuitry

Integrated circuit package with electro-optical interconnect circuitry

Integrated circuit device with field programmable optical array

Techniques for variable forward error correction

Integrated circuit device with field programmable optical array

IC package for pin counts less than test requirements

Electronic assembly apparatus and associated methods

Integrated optical-electronic interface in programmable integrated...

Systems and methods for stacking a memory chip above an integrated...

Reduced inductance IC leaded package

Ball grid array package-to-board interconnect co-design apparatus

Ball grid array package-to-board interconnect co-design apparatus

Elongated bonding pad for wire bonding and sort probing

Post-passivation thick metal pre-routing for flip chip packaging

Semiconductor package with universal substrate for electrically int...

Power plane for semiconductor device

Method for forming electronic device

Non-destructive test for inner lead bond of a tab device

System for securing and electrically connecting a semiconductor chi...

Method of providing a capacitor within a semiconductor device package

System for protecting leads of a semiconductor chip package during...

Method for bonding a lead to a die pad using an electroless plating...

Integrated circuit die-to-leadframe interconnect assembly system

System for protecting leads to a semiconductor chip package during...

Semiconductor device package having a thermal dissipation means tha...

Electronic device package--carrier assembly ready to be mounted ont...

Semiconductor chip cooling apparatus

Integrated circuit package with device and wire coat assembly

Internal capacitor arrangement for semiconductor device assembly

Heat sink for semiconductor device assembly

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT PACKAGE WITH ELECTRO-OPTICAL INTERCONNECT CIRCUITRY

INTEGRATED CIRCUIT PACKAGE WITH ELECTRO-OPTICAL INTERCONNECT CIRCUITRY

Techniques For Variable Forward Error Correction

APPARATUS FOR STACKED ELECTRONIC CIRCUITRY AND ASSOCIATED METHODS

ELECTRONIC ASSEMBLY APPARATUS AND ASSOCIATED METHODS

INTEGRATED OPTICAL-ELECTRONIC INTERFACE IN PROGRAMMABLE INTEGRATED...

Method and structure for integrated circuit package