Jon W. Byrn

Person

Fort Collins, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
On-chip power supply monitoring using a network of modulators
- Patent number 8,471,720
- Issue date Jun 25, 2013
- LSI Corporation
- Mark Franklin Turner
- G01 - MEASURING TESTING
Information Patent Grant
Programmable nanotube interconnect
- Patent number 8,415,714
- Issue date Apr 9, 2013
- LSI Corporation
- Jonathan Byrn
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Power grid optimization
- Patent number 8,336,018
- Issue date Dec 18, 2012
- LSI Corporation
- Mark F. Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for power dissipation control in a semiconducto...
- Patent number 8,239,700
- Issue date Aug 7, 2012
- LSI Corporation
- George Nation
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Sequential element low power scan implementation
- Patent number 8,209,573
- Issue date Jun 26, 2012
- LSI Corporation
- Jeff S. Brown
- G01 - MEASURING TESTING
Information Patent Grant
Granular channel width for power optimization
- Patent number 8,196,086
- Issue date Jun 5, 2012
- LSI Corporation
- Jeffrey S. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modulated clock, an IC including the modulated clock and a method o...
- Patent number 8,135,976
- Issue date Mar 13, 2012
- LSI Corporation
- Jeff S. Brown
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Efficient power management method in integrated circuit through a n...
- Patent number 8,017,512
- Issue date Sep 13, 2011
- LSI Corporation
- Jonathan Byrn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual path static timing analysis
- Patent number 7,966,592
- Issue date Jun 21, 2011
- LSI Corporation
- Jeffrey S. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable power segmentation using a nanotube structure
- Patent number 7,847,285
- Issue date Dec 7, 2010
- LSI Corporation
- Jonathan Byrn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Redistribution of current demand and reduction of power and DCAP
- Patent number 7,818,695
- Issue date Oct 19, 2010
- LSI Corporation
- Jonathan W. Byrn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Row decode driver gradient design in a memory device
- Patent number 7,787,325
- Issue date Aug 31, 2010
- LSI Corporation
- Jeffrey S. Brown
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable power management using a nanotube structure
- Patent number 7,755,111
- Issue date Jul 13, 2010
- LSI Corporation
- Jonathan Byrn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for automatic creation and placement of a floo...
- Patent number 7,703,059
- Issue date Apr 20, 2010
- LSI Corporation
- Daniel J. Murray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable power management using a nanotube structure
- Patent number 7,655,548
- Issue date Feb 2, 2010
- LSI Corporation
- Jonathan Byrn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable nanotube interconnect
- Patent number 7,494,842
- Issue date Feb 24, 2009
- LSI Corporation
- Jonathan Byrn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cell library management for power optimization
- Patent number 7,496,867
- Issue date Feb 24, 2009
- LSI Corporation
- Mark F. Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Suite of tools to design integrated circuits
- Patent number 7,430,725
- Issue date Sep 30, 2008
- LSI Corporation
- Robert Neal Carlton Broberg, III
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and computer program for management of synchronous and async...
- Patent number 7,412,678
- Issue date Aug 12, 2008
- LSI Corporation
- Juergen Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic generation of correct minimal clocking constraints for a...
- Patent number 7,380,229
- Issue date May 27, 2008
- LSI Corporation
- Jonathan W. Byrn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for abstraction of manufacturing test access and control por...
- Patent number 7,340,700
- Issue date Mar 4, 2008
- LSI Logic Corporation
- Steven Emerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Guided capture, creation, and seamless integration with scalable co...
- Patent number 7,290,224
- Issue date Oct 30, 2007
- LSI Corporation
- Jonathan Byrn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of identifying floorplan problems in an integrated circuit l...
- Patent number 7,263,678
- Issue date Aug 28, 2007
- LSI Corporation
- Jonathan W. Byrn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache line cut through of limited life data in a data processing sy...
- Patent number 7,149,218
- Issue date Dec 12, 2006
- International Business Machines Corporation
- Chad B. McBride
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process and apparatus for characterizing intellectual property for...
- Patent number 7,103,858
- Issue date Sep 5, 2006
- LSI Logic Corporation
- Jonathan W. Byrn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simplified process to design integrated circuits
- Patent number 7,055,113
- Issue date May 30, 2006
- LSI Logic Corporation
- Robert Neal Carlton Broberg, III
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for composing memory on programmable platform devices to mee...
- Patent number 6,966,044
- Issue date Nov 15, 2005
- LSI Logic Corporation
- Paul G. Reuland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Custom clock interconnects on a standardized silicon platform
- Patent number 6,910,201
- Issue date Jun 21, 2005
- LSI Logic Corporation
- Jonathan William Byrn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for automatically configuring and/or inserting...
- Patent number 6,871,154
- Issue date Mar 22, 2005
- LSI Logic Corporation
- Jonathan Byrn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement of configurable input/output buffer structures during des...
- Patent number 6,823,502
- Issue date Nov 23, 2004
- LSI Logic Corporation
- Matthew Scott Wingren
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SCALABLE POWER MODEL CALIBRATION
- Publication number 20140074449
- Publication date Mar 13, 2014
- LSI Corporation
- Mark F. Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On-chip Power Supply Monitoring Using a Network of Modulators
- Publication number 20120119788
- Publication date May 17, 2012
- Mark Franklin Turner
- G01 - MEASURING TESTING
Information Patent Application
BUILT-IN SELF-TEST CIRCUIT-BASED RADIATION SENSOR, RADIATION SENSIN...
- Publication number 20120065919
- Publication date Mar 15, 2012
- LSI Corporation
- Jeff S. Brown
- G01 - MEASURING TESTING
Information Patent Application
GRANULAR CHANNEL WIDTH FOR POWER OPTIMIZATION
- Publication number 20120023473
- Publication date Jan 26, 2012
- Jeffrey S. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER GRID OPTIMIZATION
- Publication number 20110304052
- Publication date Dec 15, 2011
- Mark F. Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT POWER MANAGEMENT METHOD IN INTEGRATED CIRCUIT THROUGH A N...
- Publication number 20110039398
- Publication date Feb 17, 2011
- LSI Corporation
- JONATHAN BYRN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Predictive Power Management Semiconductor Design Tool and Methods f...
- Publication number 20100269074
- Publication date Oct 21, 2010
- LSI CORPORATION
- George Nation
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods for Ramped Power State Control in a Semiconduct...
- Publication number 20100268917
- Publication date Oct 21, 2010
- LSI CORPORATION
- George Nation
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods for Power Dissipation Control in a Semiconducto...
- Publication number 20100264983
- Publication date Oct 21, 2010
- LSI CORPORATION
- George Nation
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEQUENTIAL ELEMENT LOW POWER SCAN IMPLEMENTATION
- Publication number 20100162058
- Publication date Jun 24, 2010
- LSI Corporation
- Jeff S. Brown
- G01 - MEASURING TESTING
Information Patent Application
MODULATED CLOCK, AN IC INCLUDING THE MODULATED CLOCK AND A METHOD O...
- Publication number 20100150271
- Publication date Jun 17, 2010
- LSI Corporation
- Jeff S. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE POWER MANAGEMENT USING A NANOTUBE STRUCTURE
- Publication number 20100090253
- Publication date Apr 15, 2010
- JONATHAN BYRN
- B82 - NANO-TECHNOLOGY
Information Patent Application
ROW DECODE DRIVER GRADIENT DESIGN IN A MEMORY DEVICE
- Publication number 20090285047
- Publication date Nov 19, 2009
- Jeffrey S. Brown
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE NANOTUBE INTERCONNECT
- Publication number 20090189196
- Publication date Jul 30, 2009
- JONATHAN BYRN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDISTRIBUTION OF CURRENT DEMAND AND REDUCTION OF POWER AND DCAP
- Publication number 20090164956
- Publication date Jun 25, 2009
- Jonathan W. Byrn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL PATH STATIC TIMING ANALYSIS
- Publication number 20090144682
- Publication date Jun 4, 2009
- Jeffrey S. Brown
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cell library management for power optimization
- Publication number 20080244474
- Publication date Oct 2, 2008
- LSI Logic Corporation
- Mark F. Turner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for automatic creation and placement of a floo...
- Publication number 20070271539
- Publication date Nov 22, 2007
- Daniel J. Murray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable power segmentation using a nanotube structure
- Publication number 20070125999
- Publication date Jun 7, 2007
- LSI Logic Corporation
- Jonathan Byrn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Programmable nanotube interconnect
- Publication number 20070114613
- Publication date May 24, 2007
- LSI Logic Corporation
- Jonathan Byrn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Programmable power management using a nanotube structure
- Publication number 20070114517
- Publication date May 24, 2007
- LSI Logic Corporation
- Jonathan Byrn
- B82 - NANO-TECHNOLOGY
Information Patent Application
Method for creating constraints for integrated circuit design closure
- Publication number 20070033557
- Publication date Feb 8, 2007
- Jonathan W. Byrn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic generation of correct minimal clocking constraints for a...
- Publication number 20060282808
- Publication date Dec 14, 2006
- LSI Logic Corporation
- Jonathan W. Byrn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for abstraction of manufacturing test access and control por...
- Publication number 20060271904
- Publication date Nov 30, 2006
- LSI Logic Corporation
- Steven M. Emerson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of identifying floorplan problems in an integrated circuit l...
- Publication number 20060218515
- Publication date Sep 28, 2006
- LSI Logic Corporation
- Jonathan W. Byrn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Guided capture, creation, and seamless integration with scalable co...
- Publication number 20050273738
- Publication date Dec 8, 2005
- LSI Logic Corporation
- Jonathan Byrn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and computer program for management of synchronous and async...
- Publication number 20050273741
- Publication date Dec 8, 2005
- Juergen Lahner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Suite of tools to design integrated circuits
- Publication number 20050240892
- Publication date Oct 27, 2005
- LSI Logic Corporation
- Robert Neal Carlton Broberg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Process and apparatus for characterizing intellectual property for...
- Publication number 20050235244
- Publication date Oct 20, 2005
- LSI Logic Corporation
- Jonathan W. Byrn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Custom clock interconnects on a standardized silicon platform
- Publication number 20050062495
- Publication date Mar 24, 2005
- LSI Logic Corporation
- Jonathan William Byrn
- G06 - COMPUTING CALCULATING COUNTING

Jon W. Byrn

Person

Patents Grantslast 30 patents

On-chip power supply monitoring using a network of modulators

Programmable nanotube interconnect

Power grid optimization

Systems and methods for power dissipation control in a semiconducto...

Sequential element low power scan implementation

Granular channel width for power optimization

Modulated clock, an IC including the modulated clock and a method o...

Efficient power management method in integrated circuit through a n...

Dual path static timing analysis

Configurable power segmentation using a nanotube structure

Redistribution of current demand and reduction of power and DCAP

Row decode driver gradient design in a memory device

Programmable power management using a nanotube structure

Method and apparatus for automatic creation and placement of a floo...

Programmable power management using a nanotube structure

Programmable nanotube interconnect

Cell library management for power optimization

Suite of tools to design integrated circuits

Method and computer program for management of synchronous and async...

Automatic generation of correct minimal clocking constraints for a...

Method for abstraction of manufacturing test access and control por...

Guided capture, creation, and seamless integration with scalable co...

Method of identifying floorplan problems in an integrated circuit l...

Cache line cut through of limited life data in a data processing sy...

Process and apparatus for characterizing intellectual property for...

Simplified process to design integrated circuits

Method for composing memory on programmable platform devices to mee...

Custom clock interconnects on a standardized silicon platform

Method and apparatus for automatically configuring and/or inserting...

Placement of configurable input/output buffer structures during des...

Patents Applicationslast 30 patents

SCALABLE POWER MODEL CALIBRATION

On-chip Power Supply Monitoring Using a Network of Modulators

BUILT-IN SELF-TEST CIRCUIT-BASED RADIATION SENSOR, RADIATION SENSIN...

GRANULAR CHANNEL WIDTH FOR POWER OPTIMIZATION

POWER GRID OPTIMIZATION

EFFICIENT POWER MANAGEMENT METHOD IN INTEGRATED CIRCUIT THROUGH A N...

Predictive Power Management Semiconductor Design Tool and Methods f...

Systems and Methods for Ramped Power State Control in a Semiconduct...

Systems and Methods for Power Dissipation Control in a Semiconducto...

SEQUENTIAL ELEMENT LOW POWER SCAN IMPLEMENTATION

MODULATED CLOCK, AN IC INCLUDING THE MODULATED CLOCK AND A METHOD O...

PROGRAMMABLE POWER MANAGEMENT USING A NANOTUBE STRUCTURE

ROW DECODE DRIVER GRADIENT DESIGN IN A MEMORY DEVICE

PROGRAMMABLE NANOTUBE INTERCONNECT

REDISTRIBUTION OF CURRENT DEMAND AND REDUCTION OF POWER AND DCAP

DUAL PATH STATIC TIMING ANALYSIS

Cell library management for power optimization

Method and apparatus for automatic creation and placement of a floo...

Configurable power segmentation using a nanotube structure

Programmable nanotube interconnect

Programmable power management using a nanotube structure

Method for creating constraints for integrated circuit design closure

Automatic generation of correct minimal clocking constraints for a...

Method for abstraction of manufacturing test access and control por...

Method of identifying floorplan problems in an integrated circuit l...

Guided capture, creation, and seamless integration with scalable co...

Method and computer program for management of synchronous and async...

Suite of tools to design integrated circuits

Process and apparatus for characterizing intellectual property for...

Custom clock interconnects on a standardized silicon platform