Jonathan Jasper

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory controller with reduced latency transaction scheduling
- Patent number 12,045,502
- Issue date Jul 23, 2024
- Xilinx, Inc.
- Ygal Arbel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing error handling operations using...
- Patent number 10,795,755
- Issue date Oct 6, 2020
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read training a memory controller
- Patent number 10,482,041
- Issue date Nov 19, 2019
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read training a memory controller
- Patent number 10,331,585
- Issue date Jun 25, 2019
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read training a memory controller
- Patent number 9,766,817
- Issue date Sep 19, 2017
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for training a control signal based on a strobe signal in a...
- Patent number 9,627,029
- Issue date Apr 18, 2017
- Intel Corporation
- Tonia G. Morris
- G11 - INFORMATION STORAGE
Information Patent Grant
Read training a memory controller
- Patent number 9,495,103
- Issue date Nov 15, 2016
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanism for achieving high memory reliability, availability and s...
- Patent number 9,229,828
- Issue date Jan 5, 2016
- Intel Corporation
- Dableena Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read training a memory controller
- Patent number 9,058,111
- Issue date Jun 16, 2015
- Intel Corporation
- Tonia G. Morris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for training a control signal based on a strobe signal in a...
- Patent number 9,025,399
- Issue date May 5, 2015
- Intel Corporation
- Tonia G. Morris
- G11 - INFORMATION STORAGE
Information Patent Grant
Read training a memory controller
- Patent number 9,021,154
- Issue date Apr 28, 2015
- Intel Corporation
- Tonia G. Morris
- G11 - INFORMATION STORAGE
Information Patent Grant
Mechanism for achieving high memory reliablity, availability and se...
- Patent number 8,914,704
- Issue date Dec 16, 2014
- Intel Corporation
- Debaleena Das
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pass through debug port on a high speed asynchronous link
- Patent number 7,328,375
- Issue date Feb 5, 2008
- Intel Corporation
- Ashish Gupta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
DRAM CONTROLLER WITH IN-LINE ECC
- Publication number 20240281325
- Publication date Aug 22, 2024
- Xilinx, Inc.
- Ygal ARBEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ TRAINING A MEMORY CONTROLLER
- Publication number 20170286330
- Publication date Oct 5, 2017
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ TRAINING A MEMORY CONTROLLER
- Publication number 20170031846
- Publication date Feb 2, 2017
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING ERROR HANDLING OPERATIONS USING...
- Publication number 20160210187
- Publication date Jul 21, 2016
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SCRAMBLING READ DATA IN A MEMORY MODULE
- Publication number 20160211973
- Publication date Jul 21, 2016
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR TRAINING A CONTROL SIGNAL BASED ON A STROBE SIGNAL IN A...
- Publication number 20150325281
- Publication date Nov 12, 2015
- Intel Corporation
- Tonia G. MORRIS
- G11 - INFORMATION STORAGE
Information Patent Application
MECHANISM FOR ACHIEVING HIGH MEMORY RELIABLITY, AVAILABILITY AND SE...
- Publication number 20150220410
- Publication date Aug 6, 2015
- DABLEENA DAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ TRAINING A MEMORY CONTROLLER
- Publication number 20150113234
- Publication date Apr 23, 2015
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ TRAINING A MEMORY CONTROLLER
- Publication number 20150113215
- Publication date Apr 23, 2015
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ TRAINING A MEMORY CONTROLLER
- Publication number 20150113235
- Publication date Apr 23, 2015
- Intel Corporation
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ TRAINING A MEMORY CONTROLLER
- Publication number 20150095565
- Publication date Apr 2, 2015
- INTEL CORPORATION
- Tonia G. MORRIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR ACHIEVING HIGH MEMORY RELIABLITY, AVAILABILITY AND SE...
- Publication number 20140006899
- Publication date Jan 2, 2014
- DEBALEENA DAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pass through debug port on a high speed asynchronous link
- Publication number 20050149705
- Publication date Jul 7, 2005
- Ashish Gupta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Jonathan Jasper

Person

Patents Grantslast 30 patents

Memory controller with reduced latency transaction scheduling

Method and apparatus for performing error handling operations using...

Read training a memory controller

Read training a memory controller

Read training a memory controller

Method for training a control signal based on a strobe signal in a...

Read training a memory controller

Mechanism for achieving high memory reliability, availability and s...

Read training a memory controller

Method for training a control signal based on a strobe signal in a...

Read training a memory controller

Mechanism for achieving high memory reliablity, availability and se...

Pass through debug port on a high speed asynchronous link

Patents Applicationslast 30 patents

DRAM CONTROLLER WITH IN-LINE ECC

READ TRAINING A MEMORY CONTROLLER

READ TRAINING A MEMORY CONTROLLER

METHOD AND APPARATUS FOR PERFORMING ERROR HANDLING OPERATIONS USING...

METHOD AND APPARATUS FOR SCRAMBLING READ DATA IN A MEMORY MODULE

METHOD FOR TRAINING A CONTROL SIGNAL BASED ON A STROBE SIGNAL IN A...

MECHANISM FOR ACHIEVING HIGH MEMORY RELIABLITY, AVAILABILITY AND SE...

READ TRAINING A MEMORY CONTROLLER

READ TRAINING A MEMORY CONTROLLER

READ TRAINING A MEMORY CONTROLLER

READ TRAINING A MEMORY CONTROLLER

MECHANISM FOR ACHIEVING HIGH MEMORY RELIABLITY, AVAILABILITY AND SE...

Pass through debug port on a high speed asynchronous link