Jonathan Parry

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic memory address write policy translation based on performanc...
- Patent number 12,248,705
- Issue date Mar 11, 2025
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Charge-sharing capacitive monitoring circuit in a multi-chip packag...
- Patent number 12,235,707
- Issue date Feb 25, 2025
- Micron Technology, Inc.
- Jonathan S. Parry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive read disturb scan
- Patent number 12,216,915
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Animesh R. Chowdhury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive throughput monitoring
- Patent number 12,204,792
- Issue date Jan 21, 2025
- Micron Technology, Inc.
- Reshmi Basu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent programming of retired wordline cells with dummy data
- Patent number 12,170,113
- Issue date Dec 17, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G11 - INFORMATION STORAGE
Information Patent Grant
Caching for multiple-level memory device
- Patent number 12,169,648
- Issue date Dec 17, 2024
- Micron Technology, Inc.
- Reshmi Basu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory module architecture to support memory error cor...
- Patent number 12,153,827
- Issue date Nov 26, 2024
- George Pax
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Host training indication for memory artificial intelligence
- Patent number 12,147,702
- Issue date Nov 19, 2024
- Micron Technology, Inc.
- Nicolas Soberanes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential data optimized sub-regions in storage devices
- Patent number 12,135,887
- Issue date Nov 5, 2024
- David Aaron Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure key update for replay protected memory blocks
- Patent number 12,132,832
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programming selective word lines during an erase operation in a mem...
- Patent number 12,131,028
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read counter adjustment for delaying read disturb scans
- Patent number 12,131,788
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Grant
Access operation status signaling for memory systems
- Patent number 12,124,322
- Issue date Oct 22, 2024
- Micron Technology, Inc.
- Qing Liang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundant array management techniques
- Patent number 12,111,724
- Issue date Oct 8, 2024
- Micron Technology, Inc.
- Chun Sum Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-tier defect scan management
- Patent number 12,105,967
- Issue date Oct 1, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Code rate as function of logical saturation
- Patent number 12,099,725
- Issue date Sep 24, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a flag to indicate whether a mapping entry points to sequenti...
- Patent number 12,099,449
- Issue date Sep 24, 2024
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Increased efficiency obfuscated logical-to-physical map management
- Patent number 12,086,077
- Issue date Sep 10, 2024
- Nadav Grosz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and system with dynamic ECC voltage and frequency
- Patent number 12,086,027
- Issue date Sep 10, 2024
- Jonathan Scott Parry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory block erase protocol
- Patent number 12,079,481
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Chun Sum Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with multiple input/output interfaces
- Patent number 12,079,479
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Chang H. Siau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Notifying memory system of host events via modulated reset signals
- Patent number 12,056,518
- Issue date Aug 6, 2024
- Micron Technology, Inc.
- Qing Liang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Completion flag for memory operations
- Patent number 12,050,773
- Issue date Jul 30, 2024
- Micron Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identification and storage of boot information at a memory system
- Patent number 12,019,884
- Issue date Jun 25, 2024
- Micron Technology, Inc.
- Luca Porzio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Padding cached data with valid data for memory flush commands
- Patent number 12,019,557
- Issue date Jun 25, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual address encoding for logical-to-physical mapping
- Patent number 12,007,903
- Issue date Jun 11, 2024
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Status check using signaling from a memory device
- Patent number 12,001,358
- Issue date Jun 4, 2024
- Micron Technology, Inc.
- Reshmi Basu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for retiring blocks of a memory system
- Patent number 12,002,531
- Issue date Jun 4, 2024
- Micron Technology, Inc.
- Deping He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storing parity during refresh operations
- Patent number 11,995,353
- Issue date May 28, 2024
- Micron Technology, Inc.
- Reshmi Basu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-layer code rate architecture for special event protection wit...
- Patent number 11,994,947
- Issue date May 28, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TECHNIQUES FOR STAGGERING DATA BURST EVENTS ACROSS CHANNELS
- Publication number 20250117162
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Liang Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SERIAL PASS-THROUGH TECHNIQUES FOR MEMORY DEVICE INTERFACES
- Publication number 20250118344
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Stephen Hanna
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY MODULE ARCHITECTURE TO SUPPORT MEMORY ERROR COR...
- Publication number 20250094080
- Publication date Mar 20, 2025
- Lodestar Licensing Group, LLC
- George Pax
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUNDANT ARRAY MANAGEMENT TECHNIQUES
- Publication number 20250086055
- Publication date Mar 13, 2025
- Micron Technology, Inc.
- Chun Sum Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONCURRENT PROGRAMMING OF RETIRED WORDLINE CELLS WITH DUMMY DATA
- Publication number 20250078932
- Publication date Mar 6, 2025
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING SELECTIVE WORD LINES DURING AN ERASE OPERATION IN A MEM...
- Publication number 20250053301
- Publication date Feb 13, 2025
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURE KEY UPDATE FOR REPLAY PROTECTED MEMORY BLOCKS
- Publication number 20250023725
- Publication date Jan 16, 2025
- Micro Technology, Inc.
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES
- Publication number 20250021250
- Publication date Jan 16, 2025
- Lodestar Licensing Group, LLC
- David Aaron Palmer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS
- Publication number 20250014655
- Publication date Jan 9, 2025
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Application
COMPLETION FLAG FOR MEMORY OPERATIONS
- Publication number 20250004640
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Giuseppe CARIELLO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSED LOGICAL-TO-PHYSICAL MAPPING FOR SEQUENTIALLY STORED DATA
- Publication number 20240427707
- Publication date Dec 26, 2024
- Lodestar Licensing Group LLC
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CODE RATE AS FUNCTION OF LOGICAL SATURATION
- Publication number 20240411459
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IDENTIFICATION AND STORAGE OF BOOT INFORMATION AT A MEMORY SYSTEM
- Publication number 20240402926
- Publication date Dec 5, 2024
- Micron Technology, Inc.
- Luca Porzio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-TIER DEFECT SCAN MANAGEMENT
- Publication number 20240402922
- Publication date Dec 5, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH A MULTIPLEXER CIRCUIT AND MULTIPLE INPUT/OUTPUT...
- Publication number 20240393952
- Publication date Nov 28, 2024
- Micron Technology, Inc.
- Chang H. Siau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEM WITH DYNAMIC ECC VOLTAGE AND FREQUENCY
- Publication number 20240394143
- Publication date Nov 28, 2024
- Lodestar Licensing Group, LLC
- Jonathan Scott Parry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY BLOCK ERASE PROTOCOL
- Publication number 20240385751
- Publication date Nov 21, 2024
- Micron Technology, Inc.
- Chun Sum Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR RETIRING BLOCKS OF A MEMORY SYSTEM
- Publication number 20240363185
- Publication date Oct 31, 2024
- Micron Technology, Inc.
- Deping He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORING PARITY DURING REFRESH OPERATIONS
- Publication number 20240354032
- Publication date Oct 24, 2024
- Micron Technology, Inc.
- Reshmi Basu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOST RECOVERY FOR A STUCK CONDITION
- Publication number 20240345750
- Publication date Oct 17, 2024
- Micron Technology, Inc.
- Deping He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PURGING DATA AT A MEMORY DEVICE
- Publication number 20240330519
- Publication date Oct 3, 2024
- Micron Technology, Inc.
- Christian M. Gyllenskog
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHALLOW HIBERNATE POWER STATE
- Publication number 20240329721
- Publication date Oct 3, 2024
- Micron Technology, Inc.
- Deping He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PADDING CACHED DATA WITH VALID DATA FOR MEMORY FLUSH COMMANDS
- Publication number 20240311309
- Publication date Sep 19, 2024
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING POWER CONSUMPTION ASSOCIATED WITH COMMUNICATING DATA IN A...
- Publication number 20240311053
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Deping He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR ASSEMBLIES WITH RECESSED INDUCTORS, AND METHODS FOR M...
- Publication number 20240304371
- Publication date Sep 12, 2024
- Micron Technology, Inc.
- Dustin L. Holloway
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL ADDRESS ENCODING FOR LOGICAL-TO-PHYSICAL MAPPING
- Publication number 20240296125
- Publication date Sep 5, 2024
- Lodestar Licensing Group LLC
- Giuseppe Cariello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER ARBITRATION FOR SYSTEMS OF ELECTRONIC COMPONENTS
- Publication number 20240288924
- Publication date Aug 29, 2024
- Micron Technology, Inc.
- Liang Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TOPOLOGY-BASED RETIREMENT IN A MEMORY SYSTEM
- Publication number 20240290411
- Publication date Aug 29, 2024
- Micron Technology, Inc.
- Chun S. Yeung
- G11 - INFORMATION STORAGE
Information Patent Application
EFFICIENT DATA MANAGEMENT FOR MEMORY SYSTEM ERROR HANDLING
- Publication number 20240289236
- Publication date Aug 29, 2024
- Micron Technology, Inc.
- Nitul Gohain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ORDERING ENTRIES OF AN INPUT COMMAND QUEUE
- Publication number 20240289052
- Publication date Aug 29, 2024
- Micron Technology, Inc.
- Jonathan S. Parry
- G06 - COMPUTING CALCULATING COUNTING

Jonathan Parry

Person

Patents Grantslast 30 patents

Dynamic memory address write policy translation based on performanc...

Charge-sharing capacitive monitoring circuit in a multi-chip packag...

Adaptive read disturb scan

Adaptive throughput monitoring

Concurrent programming of retired wordline cells with dummy data

Caching for multiple-level memory device

Non-volatile memory module architecture to support memory error cor...

Host training indication for memory artificial intelligence

Sequential data optimized sub-regions in storage devices

Secure key update for replay protected memory blocks

Programming selective word lines during an erase operation in a mem...

Read counter adjustment for delaying read disturb scans

Access operation status signaling for memory systems

Redundant array management techniques

Two-tier defect scan management

Code rate as function of logical saturation

Using a flag to indicate whether a mapping entry points to sequenti...

Increased efficiency obfuscated logical-to-physical map management

Methods and system with dynamic ECC voltage and frequency

Memory block erase protocol

Memory device with multiple input/output interfaces

Notifying memory system of host events via modulated reset signals

Completion flag for memory operations

Identification and storage of boot information at a memory system

Padding cached data with valid data for memory flush commands

Dual address encoding for logical-to-physical mapping

Status check using signaling from a memory device

Techniques for retiring blocks of a memory system

Storing parity during refresh operations

Multi-layer code rate architecture for special event protection wit...

Patents Applicationslast 30 patents

TECHNIQUES FOR STAGGERING DATA BURST EVENTS ACROSS CHANNELS

SERIAL PASS-THROUGH TECHNIQUES FOR MEMORY DEVICE INTERFACES

NON-VOLATILE MEMORY MODULE ARCHITECTURE TO SUPPORT MEMORY ERROR COR...

REDUNDANT ARRAY MANAGEMENT TECHNIQUES

CONCURRENT PROGRAMMING OF RETIRED WORDLINE CELLS WITH DUMMY DATA

PROGRAMMING SELECTIVE WORD LINES DURING AN ERASE OPERATION IN A MEM...

SECURE KEY UPDATE FOR REPLAY PROTECTED MEMORY BLOCKS

SEQUENTIAL DATA OPTIMIZED SUB-REGIONS IN STORAGE DEVICES

READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS

COMPLETION FLAG FOR MEMORY OPERATIONS

COMPRESSED LOGICAL-TO-PHYSICAL MAPPING FOR SEQUENTIALLY STORED DATA

CODE RATE AS FUNCTION OF LOGICAL SATURATION

IDENTIFICATION AND STORAGE OF BOOT INFORMATION AT A MEMORY SYSTEM

TWO-TIER DEFECT SCAN MANAGEMENT

MEMORY DEVICE WITH A MULTIPLEXER CIRCUIT AND MULTIPLE INPUT/OUTPUT...

METHODS AND SYSTEM WITH DYNAMIC ECC VOLTAGE AND FREQUENCY

MEMORY BLOCK ERASE PROTOCOL

TECHNIQUES FOR RETIRING BLOCKS OF A MEMORY SYSTEM

STORING PARITY DURING REFRESH OPERATIONS

HOST RECOVERY FOR A STUCK CONDITION

PURGING DATA AT A MEMORY DEVICE

SHALLOW HIBERNATE POWER STATE

PADDING CACHED DATA WITH VALID DATA FOR MEMORY FLUSH COMMANDS

MANAGING POWER CONSUMPTION ASSOCIATED WITH COMMUNICATING DATA IN A...

SEMICONDUCTOR ASSEMBLIES WITH RECESSED INDUCTORS, AND METHODS FOR M...

DUAL ADDRESS ENCODING FOR LOGICAL-TO-PHYSICAL MAPPING

POWER ARBITRATION FOR SYSTEMS OF ELECTRONIC COMPONENTS

TOPOLOGY-BASED RETIREMENT IN A MEMORY SYSTEM

EFFICIENT DATA MANAGEMENT FOR MEMORY SYSTEM ERROR HANDLING

ORDERING ENTRIES OF AN INPUT COMMAND QUEUE