Jonathan Rosch

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Device and method of very high density routing used with embedded m...
- Patent number 12,040,276
- Issue date Jul 16, 2024
- Intel Corporation
- Robert Alan May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device and method of very high density routing used with embedded m...
- Patent number 12,014,989
- Issue date Jun 18, 2024
- Intel Corporation
- Robert Alan May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual trace thickness for single layer routing
- Patent number 11,769,719
- Issue date Sep 26, 2023
- Intel Corporation
- Jonathan Rosch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device and method of very high density routing used with embedded m...
- Patent number 11,508,662
- Issue date Nov 22, 2022
- Intel Corporation
- Robert Alan May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Magnetic bilayer structure for a cored or coreless semiconductor pa...
- Patent number 11,495,555
- Issue date Nov 8, 2022
- Intel Corporation
- Yikang Deng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bi-layer prepreg for reduced dielectric thickness
- Patent number 11,276,618
- Issue date Mar 15, 2022
- Intel Corporation
- Jonathan Rosch
- B32 - LAYERED PRODUCTS
Information Patent Grant
Plated through hole socketing coupled to a solder ball to engage wi...
- Patent number 10,741,947
- Issue date Aug 11, 2020
- Intel Corporation
- Amruthavalli Pallavi Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-packaging for single-socketing
- Patent number 10,734,358
- Issue date Aug 4, 2020
- Intel Corporation
- Jonathan L. Rosch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer solder resists for semiconductor device package surface...
- Patent number 10,535,590
- Issue date Jan 14, 2020
- Intel Corporation
- Jonathan L. Rosch
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
DEVICE AND METHOD OF VERY HIGH DENSITY ROUTING USED WITH EMBEDDED M...
- Publication number 20240258240
- Publication date Aug 1, 2024
- Intel Corporation
- Robert Alan May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL TRACE THICKNESS FOR SINGLE LAYER ROUTING
- Publication number 20230369192
- Publication date Nov 16, 2023
- Intel Corporation
- Jonathan ROSCH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE AND METHOD OF VERY HIGH DENSITY ROUTING USED WITH EMBEDDED M...
- Publication number 20230135165
- Publication date May 4, 2023
- Intel Corporation
- Robert Alan May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE AND METHOD OF VERY HIGH DENSITY ROUTING USED WITH EMBEDDED M...
- Publication number 20220392842
- Publication date Dec 8, 2022
- Intel Corporation
- Robert Alan May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE AND METHOD OF VERY HIGH DENSITY ROUTING USED WITH EMBEDDED M...
- Publication number 20210280517
- Publication date Sep 9, 2021
- Intel Corporation
- Robert Alan May
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL TRACE THICKNESS FOR SINGLE LAYER ROUTING
- Publication number 20190393143
- Publication date Dec 26, 2019
- Intel Corporation
- Jonathan ROSCH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-PACKAGING FOR SINGLE-SOCKETING
- Publication number 20190385979
- Publication date Dec 19, 2019
- Intel Corporation
- Jonathan L. Rosch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BI-LAYER PREPREG FOR REDUCED DIELECTRIC THICKNESS
- Publication number 20190333832
- Publication date Oct 31, 2019
- Intel Corporation
- Jonathan Rosch
- B32 - LAYERED PRODUCTS
Information Patent Application
MAGNETIC BILAYER STRUCTURE FOR A CORED OR CORELESS SEMICONDUCTOR PA...
- Publication number 20190287934
- Publication date Sep 19, 2019
- Intel Corporation
- Yikang DENG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLATED THROUGH HOLE SOCKETING
- Publication number 20190214751
- Publication date Jul 11, 2019
- Amruthavalli Pallavi Alur
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYER SOLDER RESISTS FOR SEMICONDUCTOR DEVICE PACKAGE SURFACE...
- Publication number 20190206774
- Publication date Jul 4, 2019
- Intel Corporation
- Jonathan Rosch
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Jonathan Rosch

Person

Patents Grantslast 30 patents

Device and method of very high density routing used with embedded m...

Device and method of very high density routing used with embedded m...

Dual trace thickness for single layer routing

Device and method of very high density routing used with embedded m...

Magnetic bilayer structure for a cored or coreless semiconductor pa...

Bi-layer prepreg for reduced dielectric thickness

Plated through hole socketing coupled to a solder ball to engage wi...

Multi-packaging for single-socketing

Multi-layer solder resists for semiconductor device package surface...

Patents Applicationslast 30 patents

DEVICE AND METHOD OF VERY HIGH DENSITY ROUTING USED WITH EMBEDDED M...

DUAL TRACE THICKNESS FOR SINGLE LAYER ROUTING

DEVICE AND METHOD OF VERY HIGH DENSITY ROUTING USED WITH EMBEDDED M...

DEVICE AND METHOD OF VERY HIGH DENSITY ROUTING USED WITH EMBEDDED M...

DEVICE AND METHOD OF VERY HIGH DENSITY ROUTING USED WITH EMBEDDED M...

DUAL TRACE THICKNESS FOR SINGLE LAYER ROUTING

MULTI-PACKAGING FOR SINGLE-SOCKETING

BI-LAYER PREPREG FOR REDUCED DIELECTRIC THICKNESS

MAGNETIC BILAYER STRUCTURE FOR A CORED OR CORELESS SEMICONDUCTOR PA...

PLATED THROUGH HOLE SOCKETING

MULTI-LAYER SOLDER RESISTS FOR SEMICONDUCTOR DEVICE PACKAGE SURFACE...