Jong Shik Yoon

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Shallow trench isolation stress adjuster for MOS transistor
- Patent number 7,811,893
- Issue date Oct 12, 2010
- Texas Instruments Incorporated
- Jong Shik Yoon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Intentional pocket shadowing to compensate for the effects of cross...
- Patent number 7,795,085
- Issue date Sep 14, 2010
- Texas Instruments Incorporated
- Jong Shik Yoon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing gate sidewalls that avoids recessing
- Patent number 7,514,331
- Issue date Apr 7, 2009
- Texas Instruments Incorporated
- Jong Shik Yoon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a semiconductor device using a sidewall sp...
- Patent number 7,229,869
- Issue date Jun 12, 2007
- Texas Instruments Incorporated
- Jong Shik Yoon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having optimized shallow junction geometries a...
- Patent number 7,098,099
- Issue date Aug 29, 2006
- Texas Instruments Incorporated
- Brian E. Hornung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to engineer the inverse narrow width effect (INWE) in CMOS t...
- Patent number 7,045,436
- Issue date May 16, 2006
- Texas Instruments Incorporated
- Amitava Chatterjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing improved sidewall structures for use in se...
- Patent number 7,018,888
- Issue date Mar 28, 2006
- Texas Instruments Incorporated
- Brian E. Goodlin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MINIMIZING TRANSISTOR VARIATIONS DUE TO SHALLOW TRENCH ISOLATION ST...
- Publication number 20090258468
- Publication date Oct 15, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Jong Shik Yoon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
A METHOD OF MANUFACTURING GATE SIDEWALLS THAT AVOIDS RECESSING
- Publication number 20070287258
- Publication date Dec 13, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Jong Shik Yoon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Intentional pocket shadowing to compensate for the effects of cross...
- Publication number 20070287239
- Publication date Dec 13, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Jong Shik Yoon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for manufacturing a semiconductor device using a sidewall sp...
- Publication number 20060205169
- Publication date Sep 14, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Jong Shik Yoon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device having optimized shallow junction geometries a...
- Publication number 20060189066
- Publication date Aug 24, 2006
- Texas Instruments, Incorporated
- Brian E. Hornung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method to engineer the inverse narrow width effect (INWE) in CMOS t...
- Publication number 20060024910
- Publication date Feb 2, 2006
- Amitava Chatterjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for manufacturing improved sidewall structures for use in se...
- Publication number 20060024872
- Publication date Feb 2, 2006
- Texas Instruments, Incorporated
- Brian E. Goodlin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Minimizing transistor variations due to shallow trench isolation st...
- Publication number 20050233540
- Publication date Oct 20, 2005
- Texas Instruments, Incorporated
- Jong Shik Yoon
- H01 - BASIC ELECTRIC ELEMENTS

Jong Shik Yoon

Person

Patents Grantslast 30 patents

Shallow trench isolation stress adjuster for MOS transistor

Intentional pocket shadowing to compensate for the effects of cross...

Method of manufacturing gate sidewalls that avoids recessing

Method for manufacturing a semiconductor device using a sidewall sp...

Semiconductor device having optimized shallow junction geometries a...

Method to engineer the inverse narrow width effect (INWE) in CMOS t...

Method for manufacturing improved sidewall structures for use in se...

Patents Applicationslast 30 patents

MINIMIZING TRANSISTOR VARIATIONS DUE TO SHALLOW TRENCH ISOLATION ST...

A METHOD OF MANUFACTURING GATE SIDEWALLS THAT AVOIDS RECESSING

Intentional pocket shadowing to compensate for the effects of cross...

Method for manufacturing a semiconductor device using a sidewall sp...

Semiconductor device having optimized shallow junction geometries a...

Method to engineer the inverse narrow width effect (INWE) in CMOS t...

Method for manufacturing improved sidewall structures for use in se...

Minimizing transistor variations due to shallow trench isolation st...