Jongwon Lee

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for memory chip row hammer threat backpressure...
- Patent number 12,347,507
- Issue date Jul 1, 2025
- Intel Corporation
- Kuljit S. Bains
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory chip with per row activation count having error correction c...
- Patent number 12,164,373
- Issue date Dec 10, 2024
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Inline buffer for in-memory post package repair (PPR)
- Patent number 11,989,106
- Issue date May 21, 2024
- Intel Corporation
- Jongwon Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read retry to selectively disable on-die ECC
- Patent number 11,966,286
- Issue date Apr 23, 2024
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read retry to selectively disable on-die ECC
- Patent number 11,314,589
- Issue date Apr 26, 2022
- Intel Corporation
- Kuljit S. Bains
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with local cache array
- Patent number 11,144,466
- Issue date Oct 12, 2021
- Intel Corporation
- Jongwon Lee
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY CHIP WITH PER ROW ACTIVATION COUNT HAVING ERROR CORRECTION C...
- Publication number 20250077352
- Publication date Mar 6, 2025
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF POLLING ROW HAMMER (RH) INDICATOR INSIDE MEMORY
- Publication number 20220262428
- Publication date Aug 18, 2022
- Intel Corporation
- Kuljit S. BAINS
- G11 - INFORMATION STORAGE
Information Patent Application
READ RETRY TO SELECTIVELY DISABLE ON-DIE ECC
- Publication number 20220229724
- Publication date Jul 21, 2022
- Intel Corporation
- Kuljit S. BAINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CHIP WITH PER ROW ACTIVATION COUNT HAVING ERROR CORRECTION C...
- Publication number 20210365316
- Publication date Nov 25, 2021
- Intel Corporation
- Bill NALE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR MEMORY CHIP ROW HAMMER THREAT BACKPRESSURE...
- Publication number 20210264999
- Publication date Aug 26, 2021
- Intel Corporation
- Kuljit S. BAINS
- G11 - INFORMATION STORAGE
Information Patent Application
READ RETRY TO SELECTIVELY DISABLE ON-DIE ECC
- Publication number 20200278906
- Publication date Sep 3, 2020
- Intel Corporation
- Kuljit S. BAINS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INLINE BUFFER FOR IN-MEMORY POST PACKAGE REPAIR (PPR)
- Publication number 20200151070
- Publication date May 14, 2020
- Intel Corporation
- Jongwon LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH LOCAL CACHE ARRAY
- Publication number 20190286566
- Publication date Sep 19, 2019
- Intel Corporation
- Jongwon Lee
- G06 - COMPUTING CALCULATING COUNTING

Jongwon Lee

Person

Patents Grantslast 30 patents

Method and apparatus for memory chip row hammer threat backpressure...

Memory chip with per row activation count having error correction c...

Inline buffer for in-memory post package repair (PPR)

Read retry to selectively disable on-die ECC

Read retry to selectively disable on-die ECC

Memory device with local cache array

Patents Applicationslast 30 patents

MEMORY CHIP WITH PER ROW ACTIVATION COUNT HAVING ERROR CORRECTION C...

METHOD OF POLLING ROW HAMMER (RH) INDICATOR INSIDE MEMORY

READ RETRY TO SELECTIVELY DISABLE ON-DIE ECC

MEMORY CHIP WITH PER ROW ACTIVATION COUNT HAVING ERROR CORRECTION C...

METHOD AND APPARATUS FOR MEMORY CHIP ROW HAMMER THREAT BACKPRESSURE...

READ RETRY TO SELECTIVELY DISABLE ON-DIE ECC

INLINE BUFFER FOR IN-MEMORY POST PACKAGE REPAIR (PPR)

MEMORY DEVICE WITH LOCAL CACHE ARRAY