Jooi Wah WONG

Person

Bukit Mertajam, MY

People

Patents Applicationslast 30 patents

Information Patent Application
COPPER FILL FOR HEAT MANAGEMENT IN INTEGRATED CIRCUIT DEVICE
- Publication number 20240234234
- Publication date Jul 11, 2024
- Intel Corporation
- Min Suet Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED INDUCTOR OVER TRANSISTOR LAYER
- Publication number 20240234303
- Publication date Jul 11, 2024
- Intel Corporation
- Min Suet LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COPPER FILL FOR HEAT MANAGEMENT IN INTEGRATED CIRCUIT DEVICE
- Publication number 20240136243
- Publication date Apr 25, 2024
- Intel Corporation
- Min Suet Lim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED INDUCTOR OVER TRANSISTOR LAYER
- Publication number 20240136279
- Publication date Apr 25, 2024
- Intel Corporation
- Min Suet LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONNECTOR TO ELECTRICALLY COUPLE MULTIPLE SUBSTRATES
- Publication number 20240106139
- Publication date Mar 28, 2024
- Intel Corporation
- Jiun Hann SIR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHIELD TO REDUCE SUBSTRATE ELECTROMAGNETIC INTERFERENCE AND WARPAGE
- Publication number 20240006336
- Publication date Jan 4, 2024
- Intel Corporation
- Telesphor KAMGAING
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRICAL CONDUCTOR EXTENDING FROM A SURFACE OF A SUBSTRATE
- Publication number 20230420354
- Publication date Dec 28, 2023
- Intel Corporation
- Telesphor KAMGAING
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYPER DENSITY PACKAGE SUBSTRATE AND MEMORY COUPLED TO A MODIFIED SE...
- Publication number 20230420350
- Publication date Dec 28, 2023
- Intel Corporation
- Kavitha NAGARAJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SLOTTED STIFFENER FOR A PACKAGE SUBSTRATE
- Publication number 20230420384
- Publication date Dec 28, 2023
- Intel Corporation
- Kavitha NAGARAJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COPPER RINGS FOR BGA COUNT REDUCTION IN SMALL FORM FACTOR PACKAGES
- Publication number 20230420345
- Publication date Dec 28, 2023
- Intel Corporation
- Kavitha NAGARAJAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY ON PACKAGE (MOP) ARCHITECTURE
- Publication number 20230395576
- Publication date Dec 7, 2023
- Intel Corporation
- Eng Huat GOH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ON PACKAGE INTERCONNECT ARCHITECTURE FOR HIGH-SPEED MEMORY
- Publication number 20230395493
- Publication date Dec 7, 2023
- Intel Corporation
- Jooi Wah WONG
- G11 - INFORMATION STORAGE
Information Patent Application
ULTRA-LASER THOUGH HOLE (ULTH) BY MULTI-STACKED CORE CONCEPT
- Publication number 20230397333
- Publication date Dec 7, 2023
- Intel Corporation
- Eng Huat GOH
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
MEMORY PACKAGE ON EXTENDED BASE DIE OVER SOC DIE FOR PACKAGE LAYER...
- Publication number 20230395578
- Publication date Dec 7, 2023
- Intel Corporation
- Min Suet LIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOC-MEMORY INTEGRATION TO ACHIEVE SMALLEST AND THINNEST MEMORY ON P...
- Publication number 20230395577
- Publication date Dec 7, 2023
- Intel Corporation
- Eng Huat GOH
- H01 - BASIC ELECTRIC ELEMENTS

Jooi Wah WONG

Person

Patents Applicationslast 30 patents

COPPER FILL FOR HEAT MANAGEMENT IN INTEGRATED CIRCUIT DEVICE

INTEGRATED INDUCTOR OVER TRANSISTOR LAYER

COPPER FILL FOR HEAT MANAGEMENT IN INTEGRATED CIRCUIT DEVICE

INTEGRATED INDUCTOR OVER TRANSISTOR LAYER

CONNECTOR TO ELECTRICALLY COUPLE MULTIPLE SUBSTRATES

SHIELD TO REDUCE SUBSTRATE ELECTROMAGNETIC INTERFERENCE AND WARPAGE

ELECTRICAL CONDUCTOR EXTENDING FROM A SURFACE OF A SUBSTRATE

HYPER DENSITY PACKAGE SUBSTRATE AND MEMORY COUPLED TO A MODIFIED SE...

SLOTTED STIFFENER FOR A PACKAGE SUBSTRATE

COPPER RINGS FOR BGA COUNT REDUCTION IN SMALL FORM FACTOR PACKAGES

MEMORY ON PACKAGE (MOP) ARCHITECTURE

ON PACKAGE INTERCONNECT ARCHITECTURE FOR HIGH-SPEED MEMORY

ULTRA-LASER THOUGH HOLE (ULTH) BY MULTI-STACKED CORE CONCEPT

MEMORY PACKAGE ON EXTENDED BASE DIE OVER SOC DIE FOR PACKAGE LAYER...

SOC-MEMORY INTEGRATION TO ACHIEVE SMALLEST AND THINNEST MEMORY ON P...