Jorge E. Parra

Person

El Dorado Hills, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Register file for systolic array
- Patent number 12,346,694
- Issue date Jul 1, 2025
- Intel Corporation
- Chandra Gurram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual pipeline parallel systolic array
- Patent number 12,189,571
- Issue date Jan 7, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using sparsity metadata to reduce systolic array power consumption
- Patent number 12,190,158
- Issue date Jan 7, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic array of arbitrary physical and logical depth
- Patent number 12,174,783
- Issue date Dec 24, 2024
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computing efficient cross channel operations in parallel computing...
- Patent number 12,093,213
- Issue date Sep 17, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable sparse matrix multiply acceleration using systolic arrays...
- Patent number 12,039,001
- Issue date Jul 16, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse matrix multiplication acceleration mechanism
- Patent number 12,008,067
- Issue date Jun 11, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processors and graphics processing units having dot produc...
- Patent number 12,007,935
- Issue date Jun 11, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Utilizing structured sparsity in systolic arrays
- Patent number 11,977,885
- Issue date May 7, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processors and graphics processing units having dot produc...
- Patent number 11,954,063
- Issue date Apr 9, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compiler assisted register file write reduction
- Patent number 11,900,502
- Issue date Feb 13, 2024
- Intel Corporation
- Chandra S. Gurram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processors and graphics processing units having dot produc...
- Patent number 11,709,793
- Issue date Jul 25, 2023
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computing efficient cross channel operations in parallel computing...
- Patent number 11,669,490
- Issue date Jun 6, 2023
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instructions and logic for vector multiply add with zero skipping
- Patent number 11,669,329
- Issue date Jun 6, 2023
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for systolic dot product with accumulate
- Patent number 11,640,297
- Issue date May 2, 2023
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable sparse matrix multiply acceleration using systolic arrays...
- Patent number 11,636,174
- Issue date Apr 25, 2023
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processors and graphics processing units having dot produc...
- Patent number 11,361,496
- Issue date Jun 14, 2022
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for approximation using polynomials
- Patent number 11,327,754
- Issue date May 10, 2022
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compiler assisted register file write reduction
- Patent number 11,321,799
- Issue date May 3, 2022
- Intel Corporation
- Chandra S. Gurram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instructions and logic for vector multiply add with zero skipping
- Patent number 11,314,515
- Issue date Apr 26, 2022
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing reduction operations on a plura...
- Patent number 11,294,670
- Issue date Apr 5, 2022
- Intel Corporation
- Christopher J. Hughes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sharing register file usage between fused processing resources
- Patent number 11,221,848
- Issue date Jan 11, 2022
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable sparse matrix multiply acceleration using systolic arrays...
- Patent number 11,204,977
- Issue date Dec 21, 2021
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sparse matrix multiplication acceleration mechanism
- Patent number 11,188,618
- Issue date Nov 30, 2021
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computing efficient cross channel operations in parallel computing...
- Patent number 11,182,337
- Issue date Nov 23, 2021
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic for systolic dot product with accumulate
- Patent number 11,042,370
- Issue date Jun 22, 2021
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register sharing mechanism
- Patent number 10,983,794
- Issue date Apr 20, 2021
- Intel Corporation
- Guei-Yuan Lueh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accumulator pooling mechanism
- Patent number 10,839,478
- Issue date Nov 17, 2020
- Intel Corporation
- Guei-Yuan Lueh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for vector-matrix comparison
- Patent number 10,817,297
- Issue date Oct 27, 2020
- Intel Corporation
- Christopher J. Hughes
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for vector-matrix comparison
- Patent number 10,782,971
- Issue date Sep 22, 2020
- Intel Corporation
- Christopher J. Hughes
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
USING SPARSITY METADATA TO REDUCE SYSTOLIC ARRAY POWER CONSUMPTION
- Publication number 20250199863
- Publication date Jun 19, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL PIPELINE PARALLEL SYSTOLIC ARRAY
- Publication number 20250117359
- Publication date Apr 10, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH
- Publication number 20250117360
- Publication date Apr 10, 2025
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...
- Publication number 20240427847
- Publication date Dec 26, 2024
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20240362180
- Publication date Oct 31, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS
- Publication number 20240320000
- Publication date Sep 26, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED LOCAL REGISTERS FOR THREAD TEAM PROCESSING
- Publication number 20240112295
- Publication date Apr 4, 2024
- Intel Corporation
- Biju George
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINISTIC BROADCASTING FROM SHARED MEMORY
- Publication number 20240111534
- Publication date Apr 4, 2024
- Intel Corporation
- Fangwen Fu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE ENHANCEMENTS FOR DOUBLE PRECISION SYSTOLIC SUPPORT
- Publication number 20240111826
- Publication date Apr 4, 2024
- Intel Corporation
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARING REGISTER FILE USAGE BETWEEN FUSED PROCESSING RESOURCES
- Publication number 20240053985
- Publication date Feb 15, 2024
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING...
- Publication number 20230367740
- Publication date Nov 16, 2023
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR SYSTOLIC DOT PRODUCT WITH ACCUMULATE
- Publication number 20230297373
- Publication date Sep 21, 2023
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...
- Publication number 20230281272
- Publication date Sep 7, 2023
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20230195685
- Publication date Jun 22, 2023
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING REDUCTION OPERATIONS ON A PLURA...
- Publication number 20230060900
- Publication date Mar 2, 2023
- Intel Corporation
- Christopher J. HUGHES
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL PIPELINE PARALLEL SYSTOLIC ARRAY
- Publication number 20220414054
- Publication date Dec 29, 2022
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTER FILE FOR SYSTOLIC ARRAY
- Publication number 20220413851
- Publication date Dec 29, 2022
- Intel Corporation
- Chandra Gurram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING SPARSITY METADATA TO REDUCE SYSTOLIC ARRAY POWER CONSUMPTION
- Publication number 20220413924
- Publication date Dec 29, 2022
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC ARRAY HAVING SUPPORT FOR OUTPUT SPARSITY
- Publication number 20220413803
- Publication date Dec 29, 2022
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH
- Publication number 20220414053
- Publication date Dec 29, 2022
- Intel Corporation
- Jorge Parra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20220365901
- Publication date Nov 17, 2022
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTIONS AND LOGIC FOR VECTOR MULTIPLY ADD WITH ZERO SKIPPING
- Publication number 20220326953
- Publication date Oct 13, 2022
- Intel Corporation
- Supratim Pal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPILER ASSISTED REGISTER FILE WRITE REDUCTION
- Publication number 20220261949
- Publication date Aug 18, 2022
- Intel Corporation
- Chandra S. GURRAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERFORMING REDUCTION OPERATIONS ON A PLURA...
- Publication number 20220229661
- Publication date Jul 21, 2022
- Intel Corporation
- Christopher J. HUGHES
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARING REGISTER FILE USAGE BETWEEN FUSED PROCESSING RESOURCES
- Publication number 20220206795
- Publication date Jun 30, 2022
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPARSE MATRIX MULTIPLICATION ACCELERATION MECHANISM
- Publication number 20220171827
- Publication date Jun 2, 2022
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...
- Publication number 20220156343
- Publication date May 19, 2022
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20220129266
- Publication date Apr 28, 2022
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING...
- Publication number 20220058158
- Publication date Feb 24, 2022
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING...
- Publication number 20210365402
- Publication date Nov 25, 2021
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING

Jorge E. Parra

Person

Patents Grantslast 30 patents

Register file for systolic array

Dual pipeline parallel systolic array

Using sparsity metadata to reduce systolic array power consumption

Systolic array of arbitrary physical and logical depth

Computing efficient cross channel operations in parallel computing...

Scalable sparse matrix multiply acceleration using systolic arrays...

Sparse matrix multiplication acceleration mechanism

Graphics processors and graphics processing units having dot produc...

Utilizing structured sparsity in systolic arrays

Graphics processors and graphics processing units having dot produc...

Compiler assisted register file write reduction

Graphics processors and graphics processing units having dot produc...

Computing efficient cross channel operations in parallel computing...

Instructions and logic for vector multiply add with zero skipping

Instruction and logic for systolic dot product with accumulate

Scalable sparse matrix multiply acceleration using systolic arrays...

Graphics processors and graphics processing units having dot produc...

Method and apparatus for approximation using polynomials

Compiler assisted register file write reduction

Instructions and logic for vector multiply add with zero skipping

Method and apparatus for performing reduction operations on a plura...

Sharing register file usage between fused processing resources

Scalable sparse matrix multiply acceleration using systolic arrays...

Sparse matrix multiplication acceleration mechanism

Computing efficient cross channel operations in parallel computing...

Instruction and logic for systolic dot product with accumulate

Register sharing mechanism

Accumulator pooling mechanism

Method and apparatus for vector-matrix comparison

Method and apparatus for vector-matrix comparison

Patents Applicationslast 30 patents

USING SPARSITY METADATA TO REDUCE SYSTOLIC ARRAY POWER CONSUMPTION

DUAL PIPELINE PARALLEL SYSTOLIC ARRAY

SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH

SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

UTILIZING STRUCTURED SPARSITY IN SYSTOLIC ARRAYS

SHARED LOCAL REGISTERS FOR THREAD TEAM PROCESSING

DETERMINISTIC BROADCASTING FROM SHARED MEMORY

HARDWARE ENHANCEMENTS FOR DOUBLE PRECISION SYSTOLIC SUPPORT

SHARING REGISTER FILE USAGE BETWEEN FUSED PROCESSING RESOURCES

COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING...

INSTRUCTION AND LOGIC FOR SYSTOLIC DOT PRODUCT WITH ACCUMULATE

SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

METHOD AND APPARATUS FOR PERFORMING REDUCTION OPERATIONS ON A PLURA...

DUAL PIPELINE PARALLEL SYSTOLIC ARRAY

REGISTER FILE FOR SYSTOLIC ARRAY

USING SPARSITY METADATA TO REDUCE SYSTOLIC ARRAY POWER CONSUMPTION

SYSTOLIC ARRAY HAVING SUPPORT FOR OUTPUT SPARSITY

SYSTOLIC ARRAY OF ARBITRARY PHYSICAL AND LOGICAL DEPTH

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

INSTRUCTIONS AND LOGIC FOR VECTOR MULTIPLY ADD WITH ZERO SKIPPING

COMPILER ASSISTED REGISTER FILE WRITE REDUCTION

METHOD AND APPARATUS FOR PERFORMING REDUCTION OPERATIONS ON A PLURA...

SHARING REGISTER FILE USAGE BETWEEN FUSED PROCESSING RESOURCES

SPARSE MATRIX MULTIPLICATION ACCELERATION MECHANISM

SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING...

COMPUTING EFFICIENT CROSS CHANNEL OPERATIONS IN PARALLEL COMPUTING...