Jorge F. Garcia Pabon

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Tile sequencing mechanism
- Patent number 11,900,539
- Issue date Feb 13, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically enabling tiling in 3D workloads
- Patent number 11,640,693
- Issue date May 2, 2023
- Intel Corporation
- Justin DeCell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tile sequencing mechanism
- Patent number 11,250,627
- Issue date Feb 15, 2022
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically enabling tiling in 3D workloads
- Patent number 11,176,736
- Issue date Nov 16, 2021
- Intel Corporation
- Justin DeCell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically enabling tiling in 3D workloads
- Patent number 10,916,052
- Issue date Feb 9, 2021
- Intel Corporation
- Justin DeCell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single input multiple data processing mechanism
- Patent number 10,769,751
- Issue date Sep 8, 2020
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software scoreboard information and synchronization
- Patent number 10,692,170
- Issue date Jun 23, 2020
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vertex shader with primitive replication
- Patent number 10,628,910
- Issue date Apr 21, 2020
- Intel Corporation
- Tomasz Bujewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for adaptive pixel hashing for graphics proces...
- Patent number 10,546,362
- Issue date Jan 28, 2020
- Intel Corporation
- Kalyan K. Bhiravabhatla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pixel compression mechanism
- Patent number 10,430,990
- Issue date Oct 1, 2019
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single input multiple data processing mechanism
- Patent number 10,417,730
- Issue date Sep 17, 2019
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a high throughput rasterizer
- Patent number 10,410,081
- Issue date Sep 10, 2019
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software scoreboard information and synchronization
- Patent number 10,360,654
- Issue date Jul 23, 2019
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced power implementation of computer instructions
- Patent number 10,297,001
- Issue date May 21, 2019
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rasterization based on partial spans
- Patent number 10,269,154
- Issue date Apr 23, 2019
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling instructions that require adding results of a plurality of...
- Patent number 9,904,513
- Issue date Feb 27, 2018
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for adaptive pixel hashing for graphics proces...
- Patent number 9,836,809
- Issue date Dec 5, 2017
- Intel Corporation
- Kalyan K. Bhiravabhatla
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
TILE SEQUENCING MECHANISM
- Publication number 20240185527
- Publication date Jun 6, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC TILE SEQUENCING IN GRAPHIC PROCESSING
- Publication number 20230095535
- Publication date Mar 30, 2023
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POINTER DE-REFERENCING TECHNOLOGIES
- Publication number 20220414818
- Publication date Dec 29, 2022
- Intel Corporation
- Raghavendra KAMATH MIYAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OUT-OF-ORDER PIXEL SHADING AND RASTERIZATION
- Publication number 20220414967
- Publication date Dec 29, 2022
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SMALL POLYGON RASTERIZATION
- Publication number 20220383569
- Publication date Dec 1, 2022
- Intel Corporation
- Jorge Garcia Pabon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TILE SEQUENCING MECHANISM
- Publication number 20220262070
- Publication date Aug 18, 2022
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL TILING MECHANISM
- Publication number 20220198735
- Publication date Jun 23, 2022
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY ENABLING TILING IN 3D WORKLOADS
- Publication number 20220148261
- Publication date May 12, 2022
- Intel Corporation
- Justin DeCell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TILE SEQUENCING MECHANISM
- Publication number 20210407194
- Publication date Dec 30, 2021
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY ENABLING TILING IN 3D WORKLOADS
- Publication number 20210217235
- Publication date Jul 15, 2021
- Intel Corporation
- Justin DeCell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY ENABLING TILING IN 3D WORKLOADS
- Publication number 20200342662
- Publication date Oct 29, 2020
- Intel Corporation
- Justin DeCell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERTEX SHADER WITH PRIMITIVE REPLICATION
- Publication number 20200098078
- Publication date Mar 26, 2020
- Intel Corporation
- Tomasz Bujewski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE INPUT MULTIPLE DATA PROCESSING MECHANISM
- Publication number 20200043124
- Publication date Feb 6, 2020
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFTWARE SCOREBOARD INFORMATION AND SYNCHRONIZATION
- Publication number 20190362460
- Publication date Nov 28, 2019
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIXEL COMPRESSION MECHANISM
- Publication number 20190087999
- Publication date Mar 21, 2019
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ADAPTIVE PIXEL HASHING FOR GRAPHICS PROCES...
- Publication number 20180218474
- Publication date Aug 2, 2018
- Intel Corporation
- Kalyan K. Bhiravabhatla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SINGLE INPUT MULTIPLE DATA PROCESSING MECHANISM
- Publication number 20180174350
- Publication date Jun 21, 2018
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Rasterization Based on Partial Spans
- Publication number 20170178370
- Publication date Jun 22, 2017
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ADAPTIVE PIXEL HASHING FOR GRAPHICS PROCES...
- Publication number 20170091893
- Publication date Mar 30, 2017
- KALYAN K. BHIRAVABHATLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Handling Instructions that Require Adding Results of a Plurality of...
- Publication number 20160378432
- Publication date Dec 29, 2016
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED POWER IMPLEMENTATION OF COMPUTER INSTRUCTIONS
- Publication number 20160189327
- Publication date Jun 30, 2016
- Intel Corporation
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR A HIGH THROUGHPUT RASTERIZER
- Publication number 20160180585
- Publication date Jun 23, 2016
- SUBRAMANIAM MAIYURAN
- G06 - COMPUTING CALCULATING COUNTING

Jorge F. Garcia Pabon

Person

Patents Grantslast 30 patents

Tile sequencing mechanism

Dynamically enabling tiling in 3D workloads

Tile sequencing mechanism

Dynamically enabling tiling in 3D workloads

Dynamically enabling tiling in 3D workloads

Single input multiple data processing mechanism

Software scoreboard information and synchronization

Vertex shader with primitive replication

Method and apparatus for adaptive pixel hashing for graphics proces...

Pixel compression mechanism

Single input multiple data processing mechanism

Method and apparatus for a high throughput rasterizer

Software scoreboard information and synchronization

Reduced power implementation of computer instructions

Rasterization based on partial spans

Handling instructions that require adding results of a plurality of...

Method and apparatus for adaptive pixel hashing for graphics proces...

Patents Applicationslast 30 patents

TILE SEQUENCING MECHANISM

DYNAMIC TILE SEQUENCING IN GRAPHIC PROCESSING

POINTER DE-REFERENCING TECHNOLOGIES

OUT-OF-ORDER PIXEL SHADING AND RASTERIZATION

SMALL POLYGON RASTERIZATION

TILE SEQUENCING MECHANISM

HIERARCHICAL TILING MECHANISM

DYNAMICALLY ENABLING TILING IN 3D WORKLOADS

TILE SEQUENCING MECHANISM

DYNAMICALLY ENABLING TILING IN 3D WORKLOADS

DYNAMICALLY ENABLING TILING IN 3D WORKLOADS

VERTEX SHADER WITH PRIMITIVE REPLICATION

SINGLE INPUT MULTIPLE DATA PROCESSING MECHANISM

SOFTWARE SCOREBOARD INFORMATION AND SYNCHRONIZATION

PIXEL COMPRESSION MECHANISM

METHOD AND APPARATUS FOR ADAPTIVE PIXEL HASHING FOR GRAPHICS PROCES...

SINGLE INPUT MULTIPLE DATA PROCESSING MECHANISM

Rasterization Based on Partial Spans

METHOD AND APPARATUS FOR ADAPTIVE PIXEL HASHING FOR GRAPHICS PROCES...

Handling Instructions that Require Adding Results of a Plurality of...

REDUCED POWER IMPLEMENTATION OF COMPUTER INSTRUCTIONS

METHOD AND APPARATUS FOR A HIGH THROUGHPUT RASTERIZER